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UG155 March 24, 2008
Appendix C:
Calculating the DCM Fixed Phase Shift Value
R
phase shift values must be tested; increments of 4 (52, 56, 60, etc.) correspond to roughly
one DCM tap, and consequently provide an appropriate step size. It is not necessary to
characterize areas outside the working phase shift range.
At the edge of the operating phase shift range, system behavior changes dramatically. In
eight phase shift settings or fewer, the system can transition from no errors to exhibiting
errors. Checking the operational edge at a step size of two (on more than one board) refines
the typical operational phase shift range. Once the range is determined, choose the average
of the high and low working phase shift values as the default. During the production test,
Xilinx recommends that you re-examine the working range at corner case operating
conditions to determine whether any adjustments to the final phase shift setting are
needed.
You can use the FPGA Editor to generate the required test file set instead of resorting to
multiple PAR runs. Performing the test on design files that differ only in phase shift setting
prevents other variables from affecting the test results. FPGA Editor operations can even
be scripted further, reducing the effort needed to perform this characterization.
