Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
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21
UG155 March 24, 2008
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Chapter 1
Introduction
The Ethernet 1000BASE-X PCS/PMA or SGMII core is a fully verified solution that
supports Verilog HDL and VHDL. In addition, the example design provided with the core
supports both Verilog and VHDL.
This chapter introduces the Ethernet 1000BASE-X PCS/PMA or SGMII core and provides
related information, including recommended design experience, additional resources,
technical support, and methods for submitting feedback to Xilinx.
About the Core
The Ethernet 1000BASE-X PCS/PMA or SGMII core is a Xilinx CORE Generator™
IP core,
included in the latest IP Update on the Xilinx IP Center. For detailed information about the
core, see the Ethernet 100BASE-X PCS/PMA
product page
.
For information about system
requirements and licensing options, see Chapter 2, “Licensing the Core,” in the
Getting
Started Guide
.
Designs Using RocketIO Transceivers
RocketIO transceivers are defined by device family in the following way:
•
For Virtex-II Pro and Virtex-4 devices, RocketIO Multi-Gigabit Transceivers (MGT)
•
For Virtex-5 LXT and SXT devices, RocketIO GTP transceivers; Virtex-5 FXT devices,
RocketIO GTX transceivers
Recommended Design Experience
Although the Ethernet 1000BASE-X PCS/PMA or SGMII core is a fully-verified solution,
the challenge associated with implementing a complete design varies depending on the
configuration and functionality of the application. For best results, previous experience
building high-performance, pipelined FPGA designs using Xilinx implementation
software and User Constraint Files (UCF) is recommended.
Contact your local Xilinx representative for a closer review and estimation for your specific
requirements.
