Xilinx LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 User Manual Download Page 193

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Ethernet 1000BASE-X PCS/PMA or SGMII v9.1

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UG155 March 24, 2008

Integrating with the Tri-Mode Ethernet MAC Core

Figure 13-9:

Tri-Speed Ethernet MAC Extended to use an SGMII in Virtex-5 LXT/SXT

Tri-Speed

Ethernet

MAC

LogiCORE

phyemacrxd[7:0]

phyemacrxdv

phyemacrxer

emacphytxd7:0]

emacphytxen

emacphytxer

emacphymclkout

phyemacmdin

emacphymdout

emacphymdtri

Ethernet

1000BASE-X

PCS/PMA

or SGMII

LogiCORE

gmii_rxd[7:0]

gmii_rx_dv

gmii_rx_er

gmii_txd[7:0]

gmii_tx_en

gmii_tx_er

mdc

mdio_in

mdio_out

mdio_tri

connection

userclk2

RocketIO I/F

gmii_rxd_out[7:0]

gmii_rx_dv_out

gmii_rx_er_out

gmii_txd_in[7:0]

gmii_tx_en_in

gmii_tx_er_in

gmii_rxd_in[7:0]

gmii_rx_dv_in

gmii_rx_er_in

gmii_txd_out[7:0]

gmii_tx_en_out

gmii_tx_er_out

clk125m

SGMII Adaptation

module

sgmii_clk_en

speed_is_10_100

speed_is_100

speedis10100

speedis100

rxgmiimiiclk

txgmiimiiclk

corehassgmii

VCC

clientemacrxenable

clientemactxenable

sgmii_clk_r

Virtex-5

GTP

RocketIO

CLKIN

TXU

RCLK0

TXU

RCLK20

userclk2
(125 MHz)

erclk

BUFG

REFCLKOUT

component_n

lock

(Block Level from ex

mple de

ign)

clkin
(125MHz)

IBUFGDS

IPAD

brefclkp

IPAD

brefclkn

Summary of Contents for LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v9.1

Page 1: ...R LogiCORE IP Ethernet 1000BASE X PCS PMA or SGMII v9 1 User Guide UG155 March 24 2008...

Page 2: ...VENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOST DATA AND LOST PROFITS ARISING FROM OR RELATING TO YOUR USE OF THE SPECIFICATION EVE...

Page 3: ...22 Document 22 Chapter 2 Core Architecture System Overview 23 Ethernet 1000BASE X PCS PMA or SGMII Using A RocketIO Transceiver 23 Ethernet 1000BASE X PCS PMA or SGMII with Ten Bit Interface 25 Core I...

Page 4: ...IO Transceivers RocketIO Transceiver Logic 79 Virtex II Pro Devices 79 Virtex 4 FX Devices 81 Virtex 5 LXT and SXT Devices 83 Virtex 5 FXT Devices 85 Clock Sharing Across Multiple Cores with RocketIO...

Page 5: ...E X Standard 156 SGMII Standard 156 Simulating Auto Negotiation 156 Using the Auto Negotiation Interrupt 156 Chapter 11 Dynamic Switching of 1000BASE X and SGMII Standards Typical Application 157 Oper...

Page 6: ...Tri Mode Ethernet MAC to Provide SGMII or Dynamic Switching Functionality with TBI 185 Integration of the Tri Mode Ethernet MAC to Provide SGMII or Dynamic Switching Functionality using RocketIO Trans...

Page 7: ...of the Odd Case 214 Preamble Shrinkage 215 End of Frame Encoding 215 The Even Transmission case 215 Reception of the Even Case 216 The Odd Transmission Case 216 Reception of the Odd Case 217 Appendix...

Page 8: ...www xilinx com Ethernet 1000BASE X PCS PMA or SGMII v9 1 UG155 March 24 2008 R...

Page 9: ...ign 1000BASE X Standard Using TBI 47 Figure 4 3 Example Design Performing the SGMII Standard 48 Figure 4 4 Example Design Performing the SGMII Standard 49 Chapter 5 Using the Client side GMII Data Pat...

Page 10: ...P Transceivers for 1000BASE X 91 Figure 7 8 Clock Management Multiple Core Instances Virtex 5 RocketIO GTX Transceivers for 1000BASE X 93 Chapter 8 SGMII Dynamic Standards Switching with RocketIO Tran...

Page 11: ...d to use an SGMII in Virtex II Pro 189 Figure 13 8 Tri Speed Ethernet MAC Extended to Use an SGMII in Virtex 4 191 Figure 13 9 Tri Speed Ethernet MAC Extended to use an SGMII in Virtex 5 LXT SXT 193 F...

Page 12: ...www xilinx com Ethernet 1000BASE X PCS PMA or SGMII v9 1 UG155 March 24 2008 R...

Page 13: ...Negotiation 119 Table 9 3 Control Register Register 0 120 Table 9 4 Status Register Register 1 122 Table 9 5 PHY Identifier Registers 2 and 3 124 Table 9 6 Auto Negotiation Advertisement Register Regi...

Page 14: ...GMII Control Register 0 146 Table 9 31 SGMII Status Register 1 147 Table 9 32 PHY Identifier Registers 2 and 3 149 Table 9 33 SGMII Auto Negotiation Advertisement Register 4 149 Table 9 34 SGMII Exten...

Page 15: ...GUI options used to generate and customize the core Chapter 4 Designing with the Core provides general guidelines for creating designs with the core Chapter 5 Using the Client side GMII Data Path pro...

Page 16: ...ser about how to calculate the system timing requirements when using DCMs with the core Appendix D 1000BASE X State Machines serves as a reference for the basic operation of the 1000BASE X IEEE 802 3...

Page 17: ...ive material that has been omitted IOB 1 Name QOUT IOB 2 Name CLKIN Horizontal ellipsis Repetitive material that has been omitted allow block block_name loc1 loc2 locn Notations The prefix 0x or the s...

Page 18: ...20 www xilinx com Ethernet 1000BASE X PCS PMA or SGMII v9 1 UG155 March 24 2008 Preface About This Guide R...

Page 19: ...product page For information about system requirements and licensing options see Chapter 2 Licensing the Core in the Getting Started Guide Designs Using RocketIO Transceivers RocketIO transceivers are...

Page 20: ...IEEE 802 3 Serial GMII Specification CISCO SYSTEMS ENG 46158 Technical Support To obtain technical support specific to the Ethernet 1000BASE X PCS PMA or SGMII core visit www support xilinx com Questi...

Page 21: ...2008 Feedback R Document For comments or suggestions about this document please submit a WebCase from www support xilinx com Be sure to include the following information Document title Document numbe...

Page 22: ...24 www xilinx com Ethernet 1000BASE X PCS PMA or SGMII v9 1 UG155 March 24 2008 Chapter 1 Introduction R...

Page 23: ...000BASE X PCS and PMA sub layers or used to provide a GMII to SGMII bridge when used with a RocketIO transceiver RocketIO transceivers are defined in the following way For Virtex II Pro and Virtex 4 d...

Page 24: ...engine converts the sequence of ordered sets to GMII data octets by implementing the state diagrams of IEEE 802 3 figures 36 7a and 36 7b See Appendix D 1000BASE X State Machines Optional Auto Negotia...

Page 25: ...n Chapter 9 RocketIO Interface Block The RocketIO Interface Block enables the core to connect to a Virtex II Pro Virtex 4 or Virtex 5 FPGA RocketIO transceiver Ethernet 1000BASE X PCS PMA or SGMII wit...

Page 26: ...s no corruption to the frames of data TBI Block The core provides a TBI interface that should be routed to device IOBs to provide an off chip TBI Core Interfaces All ports of the core are internal con...

Page 27: ...io_in gmii_rxd 7 0 gmii_txd 7 0 gmii_tx_en mgt_rx_reset gmii_tx_er reset gmii_rx_dv gmii_rx_er GMII MDIO phyad 4 0 gtx_clk signal_detect mdio_out mdio_tri rxbufstatus 1 0 rxchariscomma rxcharisk Rocke...

Page 28: ...ut Using RocketIO Transceiver without PCS Management Registers mgt_rx_reset signal_detect rxbufstatus 1 0 rxchariscomma rxcharisk RocketIO Interface mgt_tx_reset rxclkcorcnt 2 0 rxdata 7 0 rxdisperr r...

Page 29: ...e Auto Negotiation functionality see Chapter 3 Generating and Customizing the Core Figure 2 5 Component Pinout Using the Ten Bit Interface with PCS Management Registers mdc mdio_in gmii_rxd 7 0 gmii_t...

Page 30: ...ptional PCS Management Registers Figure 2 6 Component Pinout Using Ten Bit Interface without PCS Management Registers gmii_rxd 7 0 gmii_txd 7 0 gmii_tx_en tx_code_group 9 0 rx_code_group0 9 0 gmii_tx_...

Page 31: ...internally integrated The HDL example design delivered with the core connects these signals to IOBs to provide a place and route example For more information see Designing with the Client side GMII f...

Page 32: ...put GMII Transmit control signal from MAC gmii_tx_er1 Input GMII Transmit control signal from MAC gmii_rxd 7 0 2 2 These signals are synchronous to the core s internal 125 MHz reference clock This is...

Page 33: ...k When high the link is valid synchronization of the link has been obtained and Auto Negotiation if present and enabled has successfully completed When low a valid link has not been established Either...

Page 34: ...cription mdc Input N A Management clock 2 5 MHz mdio__in1 1 These signals can be connected to a Tri state buffer to create a bidirectional mdio signal suitable for connection to an external MDIO contr...

Page 35: ...external PMA module to enter loopback mode Bit 2 Power Down When the RocketIO transceiver is used when set to 1 the MGT is placed in a low power state A reset must be applied to clear With the TBI ve...

Page 36: ...nk_timer_basex 8 0 1 1 Clock domain is userclk2 Input Used to configure the duration of the Auto Negotiation Link Timer period when performing the 1000BASE X standard The duration of this timer is set...

Page 37: ...e will use this input to hold the RocketIO transceiver in reset until the DCM obtains lock Clock domain is not applicable rxbufstatus 1 0 1 Input Connect to RocketIO signal of the same name rxcharisco...

Page 38: ...ode_group 9 0 Output gtx_clk 10 bit parallel transmit data to PMA Sublayer SERDES loc_ref Output N A Causes the PMA sublayer clock recovery unit to lock to pma_tx_clk This signal is currently tied to...

Page 39: ...Ethernet 1000BASE X PCS PMA or SGMII customization screen used to set core parameters and options For help starting and using CORE Generator on your system see the documentation included with ISE incl...

Page 40: ...a Gigabit Media Independent Interface GMII to Serial GMII SGMII bridge as defined in the Serial GMII Specification Cisco Systems ENG 46158 SGMII may be used to replace GMII at a much lower pin count a...

Page 41: ...ted the core is generated with a replacement configuration vector See Optional Configuration Vector in Chapter 9 The Management Interface is selected by default Auto Negotiation Select this option to...

Page 42: ...Chapter 3 Generating and Customizing the Core R This screen lets you select the Receiver Elastic Buffer type to be used with the core Before selecting this option see Receiver Elastic Buffer Implemen...

Page 43: ...the example design delivered with the core Depending on the option selected the example design instantiates a single core netlist and does one of the following MGT A 0 Connects to RocketIO transceive...

Page 44: ...IUS and Synopsys simulators See the Ethernet 1000BASE X PCS PMA or SGMII Getting Started Guide for a complete description of the CORE Generator output files simulation requirements and detailed inform...

Page 45: ...ot all implementations require all of the design steps defined in this chapter Carefully follow the provided logic design guidelines to ensure success Design Overview An HDL example design built aroun...

Page 46: ...nnects the physical side interface of the core to a RocketIO transceiver The top level of the example design creates a specific example that can be simulated synthesized implemented and if required pl...

Page 47: ...OBs creating an external TBI See Chapter 6 The Ten Bit Interface The top level of the example design creates a specific example that can be simulated synthesized implemented and if required placed on...

Page 48: ...om HDL Connects the physical side interface of the core to a RocketIO transceiver Connects the client side GMII of the core to an SGMII Adaptation Module which provides the functionality to operate at...

Page 49: ...ore to device IOBs creating an external TBI See Chapter 6 The Ten Bit Interface Connects the client side GMII of the core to an SGMII Adaptation Module which provides the functionality to operate at s...

Page 50: ...Run the implement script in the implement directory to create a top level netlist for the design The script may also run the Xilinx tools map par and bitgen to create a bitstream that can be download...

Page 51: ...black box to synthesis tools Create a Bitstream Run the Xilinx tools map par and bitgen to create a bitstream that can be downloaded to a Xilinx device The UCF produced by the CORE Generator should be...

Page 52: ...Use Supported Design Flows The core is pre synthesized and is delivered as an NGC netlist The example implementation scripts provided currently uses ISE 10 1 as the synthesis tool for the HDL example...

Page 53: ...trate GMII transmission In these figures the clock is not labeled The source of this clock signal varies depending on the options selected when the core is generated For more information on clocking s...

Page 54: ...the clock is not labelled The source of this clock signal will vary depending on the options used when the core is generated For more information on clocking see Chapters 6 7 and 8 Normal Frame Recep...

Page 55: ...s for more information This is not an error condition and may occur even for full duplex frames Frame Reception with Errors The signal gmii_rx_er when asserted within the assertion window signals that...

Page 56: ...ion as a Link Status LED When high the link is valid synchronization of the link has been obtained and Auto Negotiation if present and enabled has completed When low a valid link has not been establis...

Page 57: ...ransceiver CRC Functionality When the core is generated with the Virtex II Pro RocketIO transceiver the CRC functionality of the RocketIO transceiver may be enabled When the core is generated in this...

Page 58: ...s FCS field The RocketIO transceiver will assert RXCHECKINGCRC and RXCRCERR signals as defined in the Virtex II Pro RocketIO Transceiver User Guide Figure 5 9 illustrates a frame received with a corre...

Page 59: ...ical to that described in Designing with the Client side GMII for the 1000BASE X Standard 100 Megabit per Second Frame Transmission The operation of the core remains unchanged It is the responsibility...

Page 60: ...d Frame Reception The timing of normal inbound frame transfer is illustrated in Figure 5 12 At 1 Gbps speed the operation of the receiver GMII signals remains identical to that described in Designing...

Page 61: ...be used to connect to an internally integrated Media Access Controller For details see Integrating with the 1 Gigabit Ethernet MAC Core page 179 and Integrating with the Tri Mode Ethernet MAC Core pag...

Page 62: ...e input transmitter signals are registered in device IOBs before presenting them to the FPGA fabric This logic achieves the required setup and hold times Figure 5 14 GMII Transmitter Logic gmii_tx_clk...

Page 63: ...milies Phase shifting may then be applied to the DCM to fine tune the setup and hold times at the GMII IOB input flip flops The fixed phase shift is applied to the DCM with the example UCF for the exa...

Page 64: ...e IODELAY elements can be adjusted to fine tune the setup and hold times at the GMII IOB input flip flops The delay is applied to the IODELAY element using constraints in the UCF these can be edited i...

Page 65: ...lops The delay is applied to the IODELAY element using constraints in the UCF these can be edited if desired See Constraints When Implementing an External GMII in Chapter 12 for more information Figur...

Page 66: ...istered in device IOBs before driving them to the device pads The logic required to forward the receiver GMII clock is also shown This uses an IOB output Double Data Rate DDR register so that the cloc...

Page 67: ...ogic IOB LOGIC OBUFT FDDRRSE OPAD D Q 0 1 gmii_rxd_obuf 0 OPAD OPAD OPAD OBUFT OBUFT OBUFT D Q D Q D Q D Q gmii_rx_dv_obuf gmii_rx_er_obuf gmii_rxd 0 gmii_rx_dv gmii_rx_er gmii_rx_clk gmii_rx_clk_obuf...

Page 68: ...68 www xilinx com Ethernet 1000BASE X PCS PMA or SGMII v9 1 UG155 March 24 2008 Chapter 5 Using the Client side GMII Data Path R...

Page 69: ...xternal TBI The TBI logic implemented in the block level is illustrated in all the figures in this chapter Transmitter Logic Figure 6 1 illustrates the use of the physical transmitter interface of the...

Page 70: ...f both pma_rx_clk0_bufg and pma_rx_clk1_bufg pma_rx_clk0 and pma_rx_clk1 are 180 degrees out of phase with each other This splits the input TBI data bus rx_code_group 9 0 up into two buses rx_code_gro...

Page 71: ...6 2 Ten Bit Interface Receiver Logic component_name_block Block Level from example design pma_rx_clk0 IBUFG IOB LOGIC IPAD rx_code_group 0 IBUF IPAD rx_code_group_ibuf 0 D Q Ethernet 1000BASE X PCS P...

Page 72: ...the DCM to fine tune the setup and hold times at the TBI IOB input flip flops Fixed phase shift is applied to the DCM using constraints in the example UCF for the example design See Constraints When I...

Page 73: ...as illustrated Caution This logic relies on pma_rx_clk0 and pma_rx_clk1 being exactly 180 degrees out of phase with each other since the falling edge of pma_rx_clk0 is used in place of pma_rx_clk1 Se...

Page 74: ...n alternative implementation where both pma_rx_clk0 and pma_rx_clk1 are used as intended Each bit of rx_code_group 9 0 must be routed to two separate device pads Figure 6 5 Alternate Ten Bit Interface...

Page 75: ...s illustrated Caution This logic relies on pma_rx_clk0 and pma_rx_clk1 being exactly 180 degrees out of phase with each other because the falling edge of pma_rx_clk0 is used in place of pma_rx_clk1 Se...

Page 76: ...nd pma_rx_clk1 are used as intended Each bit of rx_code_group 9 0 must be routed to two separate device pads The IODELAY elements shown on Figure 6 7 can be used to compensate for any bus skew that ha...

Page 77: ...trates the receiver clock logic used for the Virtex II family See Receiver Logic page 70 for a description of the clock logic for other device families Figure 6 8 illustrates only two cores However mo...

Page 78: ...78 www xilinx com Ethernet 1000BASE X PCS PMA or SGMII v9 1 UG155 March 24 2008 Chapter 6 The Ten Bit Interface R...

Page 79: ...core from HDL Connects the physical side interface of the core to a Virtex II Pro Virtex 4 or Virtex 5 RocketIO transceiver The logic implemented in the block level is illustrated in all the figures i...

Page 80: ...BUFGDS IOB LOGIC brefclkp IPAD brefclkn brefclk 62 5MHz dcm_locked LOCKED rxbufstatus 1 0 rxchariscomma rxcharisk rxclkcorcnt 2 0 rxdata 7 0 rxdisperr powerdown txchardispmode txchardispval txcharisk...

Page 81: ...t back into the MGT on the user interface clock ports rxusrclk2 and txusrclk2 With the attribute settings applied to the MGT from the example design the txusrclk and rxusrclk ports are derived interna...

Page 82: ...1 0 rxchariscomma rxcharisk rxclkcorcnt 2 0 rxdata 7 0 rxrundisp powerdown txchardispmode txchardispval txcharisk txdata 7 0 enablealign RXBUFERR RXCHARISCOMMA RXCHARISK RXSTATUS 5 0 RXDATA 7 0 RXRUND...

Page 83: ...bal clock routing can be used by all core logic This clock is input back into the GTP transceiver on the user interface clock ports rxusrclk rxusrclk2 txusrclk and txusrclk2 See also Virtex 5 RocketIO...

Page 84: ...s 1 0 rxchariscomma rxcharisk rxclkcorcnt 2 0 rxdata 7 0 rxrundisp powerdown txchardispmode txchardispval txcharisk txdata 7 0 enablealign RXBUFERR0 RXCHARISCOMMA0 RXCHARISK0 RXCLKCORCNT 2 0 RXDATA 07...

Page 85: ...core logic this clock is also input back into the GTX transceiver on the user interface clock ports rxusrclk2 and txusrclk2 From the DCM the CLKDV port 62 5MHz is placed onto global clock routing and...

Page 86: ...charisk rxclkcorcnt 2 0 rxdata 7 0 rxrundisp powerdown txchardispmode txchardispval txcharisk txdata 7 0 enablealign RXBUFERR0 RXCHARISCOMMA0 RXCHARISK0 RXCLKCORCNT 2 0 RXDATA 07 0 RXRUNDISP0 POWERDOW...

Page 87: ...the fixed routing resources of brefclk MGTs along the top edge of the device must use a separate brefclk routing resource to those along the bottom edge of the device For more information see the Vir...

Page 88: ...otal More cores can be added by continuing to instantiate extra block level modules Share clocks only between the MGTs in a single column For each column use a single brefclk_p and brefclk_n different...

Page 89: ...x 4 GT11 RocketIO B REFCLK1 TXOUTCLK1 Ethernet 1000BASE X PCS PMA or SGMII core userclk userclk2 NC userclk2 125 MHz BUFG TXUSRCLK TXUSRCLK2 RXUSRCLK RXUSRCLK2 TXUSRCLK TXUSRCLK2 RXUSRCLK RXUSRCLK2 sy...

Page 90: ...sent in a GTP tile Figure 7 7 illustrates two instantiations of the block level and each block level contains a pair of cores consequently illustrating clock sharing between a total of four cores Addi...

Page 91: ...or SGMII core userclk userclk2 userclk2 125 MHz BUFG TXUSRCLK0 TXUSRCLK20 RXUSRCLK0 RXUSRCLK20 TXUSRCLK1 TXUSRCLK21 RXUSRCLK1 RXUSRCLK21 clkin 125MHz REFCLKOUT component_name_block Block Level Ethern...

Page 92: ...nstantiations of the block level and each block level contains a pair of cores consequently illustrating clock sharing between a total of four cores Additional cores can be added by continuing to inst...

Page 93: ...userclk2 TXUSRCLK0 TXUSRCLK20 RXUSRCLK0 RXUSRCLK20 TXUSRCLK1 TXUSRCLK21 RXUSRCLK1 RXUSRCLK21 clkin 125MHz REFCLKOUT component_name_block Block Level Ethernet 1000BASE X PCS PMA or SGMII core userclk...

Page 94: ...94 www xilinx com Ethernet 1000BASE X PCS PMA or SGMII v9 1 UG155 March 24 2008 Chapter 7 1000BASE X with RocketIO Transceivers R...

Page 95: ...iations of the core are required when using the fabric Receiver Elastic Buffer are then presented Clock sharing should occur whenever possible to save device resources Receiver Elastic Buffer Implemen...

Page 96: ...x Elastic Buffer to half full occupancy This is performed by the clock correction circuitry see the RocketIO User Guide for the targeted device Analysis Assuming separate clock sources each of toleran...

Page 97: ...non jumbo frames the RocketIO Elastic Buffer must be bypassed and a larger buffer implemented in the FPGA fabric The fabric buffer provided by the example design is twice the size of the RocketIO alt...

Page 98: ...with the following exception assume that the clock sources used are both 50 ppm Now the maximum frequency difference between the two devices is 100 ppm It can be shown that this translates into a ful...

Page 99: ...e to the MGT For example REFCLK may be used instead of BREFCLK See the Virtex II Pro RocketIO Transceiver User Guide UG024 for details Figure 8 3 shows that the Rx Elastic Buffer is implemented in the...

Page 100: ...0 POWERDOWN TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA 7 0 BREFCLK REFCLK2 REFCLK REFCLKSEL NC NC NC GND ENPCOMMAALIGN ENMCOMMAALIGN D Q RXRECCLK RXPOLARITY TXPOLARITY TXFORCECRCERR TXINHIBIT GND G...

Page 101: ...A fabric It can be seen from Figure 8 4 that the Rx Elastic Buffer is implemented in the FPGA fabric between the MGT and the core This replaces the Rx Elastic Buffer in the MGT which is bypassed This...

Page 102: ...TXUSRCLK TXUSRCLK2 RXUSRCLK RXUSRCLK2 userclk userclk2 IPAD IPAD brefclkn 250 MHz rxbufstatus 1 0 rxchariscomma rxcharisk rxclkcorcnt 2 0 rxdata 7 0 rxrundisp powerdown txchardispmode txchardispval tx...

Page 103: ...ne present in the GTP transceiver It is able to cope with larger frame sizes before clock tolerances accumulate and result in emptying or filling of the buffer This is necessary to guarantee SGMII ope...

Page 104: ...riscomma rxcharisk rxclkcorcnt 2 0 rxdata 7 0 rxrundisp powerdown txchardispmode txchardispval txcharisk txdata 7 0 enablealign RXCHARISCOMMA0 RXCHARISK0 RXDATA0 7 0 RXRUNDISP0 POWERDOWN0 TXCHARDISPMO...

Page 105: ...is replaces the Rx Elastic Buffer in the GTX transceiver This alternative Receiver Elastic Buffer uses a single block RAM to create a buffer twice as large as the one present in the GTX transceiver It...

Page 106: ...clk2 rxbufstatus 1 0 rxchariscomma rxcharisk rxclkcorcnt 2 0 rxdata 7 0 rxrundisp powerdown txchardispmode txchardispval txcharisk txdata 7 0 enablealign RXCHARISCOMMA0 RXCHARISK0 RXDATA0 7 0 RXRUNDIS...

Page 107: ...ing the block level from the example design and sharing userclk userclk2 and brefclk across all instantiations For each core userclk and userclk2 must always be derived from the brefclk or refclk used...

Page 108: ...th Virtex II Pro RocketIO Transceivers for SGMII DCM CLKIN CLK0 CLK2X180 FB BUFG BUFG IBUFGDS TXUSRCLK BREFCLK TXUSRCLK2 RXUSRCLK RXUSRCLK2 GT_CUSTOM brefclk 62 5MHz userclk 62 5 MHz userclk2 125 MHz...

Page 109: ...ks only between the MGTs in a single column For each column use a single brefclk_p and brefclk_n differential clock pair and connect this to a GT11CLK_MGT primitive The clock output from this primitiv...

Page 110: ...erclk2 NC userclk2 125 MHz TXUSRCLK TXUSRCLK2 RXUSRCLK RXUSRCLK2 synclk1 250MHz 0 0 0 0 TXOUTCLK1 RXRECCLK1 FPGA fabric Rx Elastic Buffer BUFR Virtex 4 GT11 RocketIO B REFCLK1 TXUSRCLK TXUSRCLK2 RXUSR...

Page 111: ...el contains a pair of cores Figure 8 9 illustrates clock sharing between four cores More cores can be added by instantiating extra block level modules Share the brefclk_p and brefclk_n differential cl...

Page 112: ...K0 FPGA fabric Rx Elastic Buffer BUFR Virtex 5 GTP RocketIO 1 TXUSRCLK1 TXUSRCLK21 RXUSRCLK1 RXUSRCLK21 RXRECCLK1 FPGA fabric Rx Elastic Buffer BUFR BUFG component_name_block Block Level Ethernet 1000...

Page 113: ...strates clock sharing between four cores More cores can be added by instantiating extra block level modules Share the brefclk_p and brefclk_n differential clock pairs See the Virtex 5 RocketIO GTX Tra...

Page 114: ...Virtex 5 GTP RocketIO 1 TXUSRCLK1 TXUSRCLK21 RXUSRCLK1 RXUSRCLK21 RXRECCLK1 FPGA fabric Rx Elastic Buffer BUFR component_name_block Block Level Ethernet 1000BASE X PCS PMA or SGMII core userclk usercl...

Page 115: ...nfiguration and status of the core is achieved by the Management Registers accessed through the serial Management Data Input Output Interface MDIO See MDIO Management Interface in Chapter 3 for more i...

Page 116: ...MDIO master All MDIO slave devices when addressed must respond MDIO transactions take the form of an MDIO frame containing fields for transaction type address and data This MDIO frame is transferred...

Page 117: ...ddress PHYAD and Register Address REGAD Physical Address PHYAD As shown in Figure 9 1 two PHY devices are attached to the MDIO bus Each of these has a different physical address To address the intende...

Page 118: ...rame is a 5 bit binary value capable of addressing 32 unique addresses The first 16 of these registers 0 to 15 are defined by the IEEE 802 3 The remaining 16 registers 16 to 31 are reserved for PHY ve...

Page 119: ...he Optional Auto Negotiation SGMII Standard without the Optional Auto Negotiation Both 1000BASE X and SGMII Standards 1000BASE X Standard Using the Optional Auto Negotiation More information on the 10...

Page 120: ...to Negotiation Continued Register Address Register Name MDIO Register 0 Control Register Table 9 3 Control Register Register 0 Bit s Name Description Attributes Default Value 0 15 Reset 1 Core Reset 0...

Page 121: ...ect Read write 0 0 10 Isolate 1 Electrically Isolate PHY from GMII 0 Normal operation Read write 1 0 9 Restart Auto Negotiation 1 Restart Auto Negotiation Process 0 Normal Operation Read write Self cl...

Page 122: ...uplex Always returns a 0 as 100BASE T2 full duplex is not supported Returns 0 0 1 9 100BASE T2 Half Duplex Always returns a 0 as 100BASE T2 Half Duplex is not supported Returns 0 0 1 8 Extended Status...

Page 123: ...nded register set is supported Returns 0 0 1 When high the link is valid synchronization of the link has been obtained and Auto Negotiation if present and enabled has completed When low a valid link h...

Page 124: ...dvertisement Table 9 6 Auto Negotiation Advertisement Register Register 4 Bit s Name Description Attributes Default Value 4 15 Next Page 1 Next Page functionality is advertised 0 Next Page functionali...

Page 125: ...Base Table 9 7 Auto Negotiation Link Partner Ability Base Register Register 5 Bit s Name Description Attributes Default Value 5 15 Next Page 1 Next Page functionality is supported 0 Next Page functio...

Page 126: ...Name Description Attributes Default Value MDIO Register 6 Auto Negotiation Expansion Table 9 8 Auto Negotiation Expansion Register Register 6 Bit s Name Description Attributes Default Value 6 15 3 Res...

Page 127: ...1 Toggle Value toggles between subsequent Next Pages read only 0 7 10 0 Message Unformatte d Code Field Message Code Field or Unformatted Page Encoding as dictated by 7 13 read write 00000000001 Null...

Page 128: ...tatus Register Table 9 11 Extended Status Register Register 15 Bit s Name Description Attributes Default Value 15 15 1000BASE X Full Duplex Always returns a 1 for this bit since 1000BASE X Full Duplex...

Page 129: ...trol Register Register 16 Bit s Name Description Attributes Default Value 16 15 2 Reserved Always return 0s returns 0s 00000000000000 16 1 Interrupt Status 1 Interrupt is asserted 0 Interrupt is not a...

Page 130: ...loopback mode See Loopback page 197 read write 0 0 13 Speed Selection LSB Always returns a 0 for this bit Together with bit 0 6 speed selection of 1000 Mbps is identified returns 0 0 0 12 Auto Negoti...

Page 131: ...gister 1 Status Register Table 9 15 Status Register Register 1 Bit s Name Description Attributes Default Value 1 15 100BASE T4 Always returns a 0 for this bit since 100BASE T4 is not supported returns...

Page 132: ...rns 0 0 1 2 Link Status1 1 Link is up 0 Link is down Latches 0 if Link Status goes down Clears to current Link Status on read See table note for Link Status behavior read only self clearing on read 0...

Page 133: ...que Identifier Always return 0s returns 0s 0000000000000000 3 15 10 Organizationally Unique Identifier Always return 0s returns 0s 000000 3 9 4 Manufacturer s model number Always return 0s returns 0s...

Page 134: ...eturns a 1 since 1000BASE X Full Duplex is supported returns 1 1 15 14 1000BASE X Half Duplex Always returns a 0 since 1000BASE X Half Duplex is not supported returns 0 0 15 13 1000BASE T Full Duplex...

Page 135: ...in the register descriptions Registers at undefined addresses are read only and return 0s Register 0 SGMII Control Table 9 18 MDIO Registers for 1000BASE X with Auto Negotiation Register Address Regis...

Page 136: ...s 0 0 0 12 Auto Negotiation Enable 1 Enable SGMII Auto Negotiation Process 0 Disable SGMII Auto Negotiation Process read write 1 0 11 Power Down 1 Power down 0 Normal operation With the PMA option whe...

Page 137: ...use 100BASE X Half Duplex is not supported returns 0 0 1 12 10 Mbps Full Duplex Always returns a 0 for this bit because 10 Mbps Full Duplex is not supported returns 0 0 1 11 10 Mbps Half Duplex Always...

Page 138: ...ead See table note for SGMII Link Status behavior read only self clearing on read 0 1 1 Jabber Detect Always returns a 0 for this bit since Jabber Detect is not supported returns 0 0 1 0 Extended Capa...

Page 139: ...0000000 3 15 10 Organizationally Unique Identifier Always return 0s returns 0s 000000 3 9 4 Manufacturer s model number Always return 0s returns 0s 000000 3 3 0 Revision Number Always return 0s return...

Page 140: ...me Description Attributes Default Value 5 15 PHY Link Status This refers to the link status of the PHY with its link partner across the Medium 1 Link Up 0 Link Down read only 1 5 14 Acknowle dge Used...

Page 141: ...ble returns 1 1 6 1 Page Received 1 A new page has been received 0 A new page has not been received read only self clearing on read 0 6 0 Reserved Always return 0s returns 0s 0000000 NEXT PAGE ABLE PA...

Page 142: ...er 8 SGMII Next Page Receive Table 9 26 SGMII Auto Negotiation Next Page Receive Register 8 Bit s Name Description Attributes Default Value 8 15 Next Page 1 Additional Next Page s will follow 0 Last p...

Page 143: ...x is supported returns 1 1 15 14 1000BASE X Half Duplex Always returns a 0 for this bit since 1000BASE X Half Duplex is not supported returns 0 0 15 13 1000BASE T Full Duplex Always returns a 0 for th...

Page 144: ...5 2 Reserved Always return 0s returns 0s 00000000000000 16 1 Interrupt Status 1 Interrupt is asserted 0 Interrupt is not asserted If the interrupt is enabled this bit is asserted on completion of an A...

Page 145: ...elf is not directly available when SGMII Auto Negotiation is not present For this reason the status of the link and the results of the PHYs Auto Negotiation for example Speed and Duplex mode must be o...

Page 146: ...s 0 0 0 12 Auto Negotiation Enable 1 Enable SGMII Auto Negotiation Process 0 Disable SGMII Auto Negotiation Process read write 1 0 11 Power Down 1 Power down 0 Normal operation With the PMA option whe...

Page 147: ...use 100BASE X Half Duplex is not supported returns 0 0 1 12 10 Mbps Full Duplex Always returns a 0 for this bit because 10 Mbps Full Duplex is not supported returns 0 0 1 11 10 Mbps Half Duplex Always...

Page 148: ...g on read 0 1 1 Jabber Detect Always returns a 0 for this bit since Jabber Detect is not supported returns 0 0 1 0 Extended Capability Always returns a 0 for this bit because no extended register set...

Page 149: ...3 15 10 Organizationally Unique Identifier Always return 0s returns 0s 000000 3 9 4 Manufacturer s model number Always return 0s returns 0s 000000 3 3 0 Revision Number Always return 0s returns 0s 00...

Page 150: ...ptional Auto Negotiation or SGMII Standard without the Optional Auto Negotiation This register may be written to at any time See Chapter 11 Dynamic Switching of 1000BASE X and SGMII Standards for more...

Page 151: ...gure 9 5 Dynamic Switching Register 17 Table 9 35 Vendor specific Register Standard Selection Register Register 17 Bit s Name Description Attributes Default Value 17 15 1 Reserved Always return 0s Ret...

Page 152: ...ently unused Bit 1 Loopback Control When used with a RocketIO transceiver the core is placed in internal loopback mode With the TBI version Bit 1 is connected to ewrap When set to 1 this indicates to...

Page 153: ...n considering Auto Negotiation between two connected devices it must be remembered that Auto Negotiation must be either enabled in both devices or Auto Negotiation must be disabled in both devices 100...

Page 154: ...signaling Duplex Mode Flow Control capabilities for the attached MAC 3 The advertised abilities of the Link Partner are simultaneously transferred into the Auto Negotiation Link Partner Ability Base R...

Page 155: ...is the only Auto Negotiation observed by the core This SGMII Auto Negotiation function summarized previously leverages the 1000BASE X PCS PMA Auto Negotiation function but contains two differences Th...

Page 156: ...and 10 387 milliseconds SGMII Standard The Link Timer is defined as having a duration of 1 6 milliseconds The example design delivered with the core sets the binary value to 000110010 50 decimal This...

Page 157: ...I standards The FPGA is shown connected to an external off the shelf PHY with the ability to perform both BASE X and BASE T standards The core must operate in 1000BASE X mode to use the optical fibre...

Page 158: ...terpreted according to 1000BASE X Standard Using the Optional Auto Negotiation page 119 Core set to SGMII standard Management Registers 0 through 16 should be interpreted according to SGMII Standard U...

Page 159: ...ue placed on this port is sampled at the beginning of the Auto Negotiation cycle by the Link Timer when the core is set to perform the 1000BASE X standard link_timer_sgmii 8 0 The value placed on this...

Page 160: ...160 www xilinx com Ethernet 1000BASE X PCS PMA or SGMII v9 1 UG155 March 24 2008 Chapter 11 Dynamic Switching of 1000BASE X and SGMII Standards R...

Page 161: ...ces When selecting a device be aware of the following considerations Device must be large enough to accommodate the core Device must contain a sufficient number of IOBs 4 speed grade for Virtex II Spa...

Page 162: ...50 Setting MGT Attributes MGT attributes can be set by either of these methods Directly from HDL source code during MGT instantiation see the HDL source code for the example design From the UCF Attri...

Page 163: ...hen written into the replacement Rx Elastic Buffer implemented in the FPGA fabric See Chapter 8 Virtex II Pro Devices for more information about this logic For correct operation rxrecclk must be place...

Page 164: ...design See also Virtex 4 FX Devices in Chapter 7 Clock Period Constraints The clock txoutclk is provided by the MGT for use in the FPGA fabric It is connected to global clock routing to produce the u...

Page 165: ...cription of the example design provided with the core This HDL transceiver wrapper file was initially created using Architecture Wizard See the Virtex 4 FPGA RocketIO Multi Gigabit Transceiver User Gu...

Page 166: ...th the core Sections from the UCF are copied into the following descriptions to serve as examples and should be studied with the HDL source code for the example design See also Virtex 5 LXT and SXT De...

Page 167: ...he standard case These can be found in the rocketio_wrapper_gtp_tile vhd file for VHDL design entry or the rocketio_wrapper_gtp_tile v file for Verilog design entry these files were generated using th...

Page 168: ...vered receiver data signals leaving the transceiver This data is then written into the replacement Rx Elastic Buffer implemented in the FPGA fabric See Virtex 5 FXT Devices for SGMII or Dynamic Standa...

Page 169: ...UT ENCODER LOOK_UP_TABLE TNM codec8b10b TIMESPEC ts_ffs_to_codec8b10b FROM FFS TO codec8b10b 8000 ps TIMESPEC ts_codec8b10b_to_ffs FROM codec8b10b TO FFS 8000 ps Ten Bit Interface IOB Constraints The...

Page 170: ...ilies have input delay elements always of a fixed delay These are also automatically inserted by the Xilinx tools and are set to provide a zero hold time These input delays automatically meet input se...

Page 171: ...uting A fixed tap delay is applied to delay the pma_rx_clk0 clock so that it correctly samples the TBI data at the IOB IDDR register thereby meeting TBI setup and hold timing The tap delays are applie...

Page 172: ..._rx_data IDELAY_VALUE 0 INST core_wrapper tbi_rx_data_bus 2 delay_tbi_rx_data IDELAY_VALUE 0 INST core_wrapper tbi_rx_data_bus 1 delay_tbi_rx_data IDELAY_VALUE 0 INST core_wrapper tbi_rx_data_bus 0 de...

Page 173: ...true INST gmii_rx_dv_obuf IOB true INST gmii_rx_er_obuf IOB true The GMII is a 3 3 volt signal level interface The 3 3 volt LVTTL SelectIO standard is the default for Virtex II devices The following c...

Page 174: ...et to provide a zero hold time These input delays will automatically meet input setup and hold timing on the GMII without any specific constraints Spartan 3 Spartan 3E and Spartan 3A devices Figure 5...

Page 175: ...INST gmii_data_bus 6 delay_gmii_txd IOBDELAY_VALUE 53 INST gmii_data_bus 5 delay_gmii_txd IOBDELAY_VALUE 53 INST gmii_data_bus 4 delay_gmii_txd IOBDELAY_VALUE 53 INST gmii_data_bus 3 delay_gmii_txd IO...

Page 176: ...Spartan 3A DSP The results are self explanatory and show an obvious correlation and relationship to Figure 12 2 and Figure 12 3 The following example shows the GMII report from a Virtex II device The...

Page 177: ..._tx_clk_bufg 0 000 gmii_txd 7 6 513 R 7 889 R gmii_tx_clk_bufg 0 000 The implementation requires 6 501 ns of setup Figure 12 4 illustrates that this represents a figure of 1 499 ns relative to the fol...

Page 178: ...178 www xilinx com Ethernet 1000BASE X PCS PMA or SGMII v9 1 UG155 March 24 2008 Chapter 12 Constraining the Core R...

Page 179: ...tion of the 1 Gigabit Ethernet MAC to 1000BASE X PCS with TBI Figure 13 1 illustrates the connections and clock management logic required to interface the Ethernet 1000BASE X PCS PMA or SGMII core whe...

Page 180: ...et MAC LogiCORE gmii_rx_clk gmii_rxd 7 0 gmii_rx_dv gmii_rx_er gmii_txd 7 0 gmii_tx_en gmii_tx_er gtx_clk mdc mdio_in mdio_out mdio_tri Ethernet 1000BASE X PCS PMA or SGMII LogiCORE gmii_rxd 7 0 gmii_...

Page 181: ...ween the two cores Figure 13 2 1 Gigabit Ethernet MAC Extended to Include 1000BASE X PCS and PMA Using a Virtex II Pro MGT 1 Gigabit Ethernet MAC LogiCORE gmii_rx_clk gmii_rxd 7 0 gmii_rx_dv gmii_rx_e...

Page 182: ...Figure 13 2 illustrates the connections and clock management logic required to interface the Ethernet 1000BASE X PCS PMA or SGMII core when used in 1000BASE X mode to the 1 Gigabit Ethernet MAC core...

Page 183: ...f the 1 Gigabit Ethernet MAC core now operate in the same clock domain Virtex 5 LXT and SXT Devices Figure 13 4 illustrates the connections and clock management logic required to interface the Etherne...

Page 184: ...thernet MAC core now operate in the same clock domain Virtex 5 FXT Devices Figure 13 5 illustrates the connections and clock management logic required to interface the Ethernet 1000BASE X PCS PMA or S...

Page 185: ...lastic Buffer internal to the GTP transceiver should be used to save device resources Additionally when operating at 1 Gbps only the SGMII Adaptation Module instantiated from within the block level of...

Page 186: ...CS PMA or SGMII core Due to the Receiver Elastic Buffer in the core the entire GMII transmitter and receiver paths is synchronous to a single clock domain Therefore the txcoreclk and rxcoreclk inputs...

Page 187: ...CORE gmii_rxd 7 0 gmii_rx_dv gmii_rx_er gmii_txd 7 0 gmii_tx_en gmii_tx_er mdc mdio_in mdio_out mdio_tri no connection userclk2 gtx_clk gmii_rxd_out 7 0 gmii_rx_dv_out gmii_rx_er_out gmii_txd_in 7 0 g...

Page 188: ...e SGMII standard can be used to interface the two cores If both cores have been generated with the optional management interface the MDIO port can be connected to that of the Tri Speed Ethernet MAC co...

Page 189: ...mdio_in mdio_out mdio_tri Virtex II Pro RocketIO GT_CUSTOM brefclk txusrclk txusrclk2 no connection userclk userclk2 RocketIO I F DCM CLKIN CLK0 FB BUFG CLK2X180 BUFG userclk 62 5MHz userclk2 125MHz I...

Page 190: ...he MDIO port can be connected up to that of the Tri Speed Ethernet MAC core allowing the MAC to access the embedded configuration and status registers of the Ethernet 1000BASE X PCS PMA or SGMII core...

Page 191: ..._in mdio_out mdio_tri no connection userclk2 RocketIO I F gmii_rxd_out 7 0 gmii_rx_dv_out gmii_rx_er_out gmii_txd_in 7 0 gmii_tx_en_in gmii_tx_er_in gmii_rxd_in 7 0 gmii_rx_dv_in gmii_rx_er_in gmii_tx...

Page 192: ...face the MDIO port can be connected up to that of the Tri Speed Ethernet MAC core allowing the MAC to access the embedded configuration and status registers of the Ethernet 1000BASE X PCS PMA or SGMII...

Page 193: ...d 7 0 gmii_tx_en gmii_tx_er mdc mdio_in mdio_out mdio_tri no connection userclk2 RocketIO I F gmii_rxd_out 7 0 gmii_rx_dv_out gmii_rx_er_out gmii_txd_in 7 0 gmii_tx_en_in gmii_tx_er_in gmii_rxd_in 7 0...

Page 194: ...the MDIO port can be connected up to that of the Tri Speed Ethernet MAC core allowing the MAC to access the embedded configuration and status registers of the Ethernet 1000BASE X PCS PMA or SGMII cor...

Page 195: ...x_er mdc mdio_in mdio_out mdio_tri no connection userclk2 RocketIO I F gmii_rxd_out 7 0 gmii_rx_dv_out gmii_rx_er_out gmii_txd_in 7 0 gmii_tx_en_in gmii_tx_er_in gmii_rxd_in 7 0 gmii_rx_dv_in gmii_rx_...

Page 196: ...196 www xilinx com Ethernet 1000BASE X PCS PMA or SGMII v9 1 UG155 March 24 2008 Chapter 13 Interfacing to Other Cores R...

Page 197: ...t in the configuration_vector if using the core without the optional Management Interface The low power state can only be removed by issuing the core with a reset by driving the reset port of the core...

Page 198: ...Idle code groups that are transmitted through the MGT or GTP transceiver in accordance with the IEEE 802 3 specification Earlier versions before v5 0 of the core implemented loopback differently The s...

Page 199: ...5 March 24 2008 Loopback R Figure 14 2 Loopback Implementation When Using the Core with RocketIO Transceivers Ethernet 1000BASE X PCS PMA or SGMII Core RocketIO Transceiver Tx Rx FPGA Loopback occurs...

Page 200: ...200 www xilinx com Ethernet 1000BASE X PCS PMA or SGMII v9 1 UG155 March 24 2008 Chapter 14 Special Design Considerations R...

Page 201: ...Guide included in your Xilinx software installation The model is provided in the CORE Generator project directory VHDL Design Entry component_name vhd Verilog Design Entry component_name v This model...

Page 202: ...ired synthesis options To synthesize the design run xst ifn top_level_module_name scr See the XST User Guide for more information on creating project and synthesis script files and running the xst pro...

Page 203: ...en command must be executed to create the configuration bitstream BIT file based on the contents of a physical implementation file NCD The BIT file defines the behavior of the programmed FPGA An examp...

Page 204: ...n compliant simulator ModelSim v6 3c is currently supported For a SWIFT compliant simulator Cadence IUS v6 1 and Synopsys Synopsys VCS 2006 06 SP1 are currently supported Virtex 4 and Virtex II Pro De...

Page 205: ...cketIO transceiver and performing the 1000BASE X standard was tested with the 1 Gigabit Ethernet MAC core from Xilinx This follows the architecture shown in Figure 13 2 A test platform was built aroun...

Page 206: ...206 www xilinx com Ethernet 1000BASE X PCS PMA or SGMII v9 1 UG155 March 24 2008 Appendix A Core Verification Compliance and Interoperability R...

Page 207: ...TBI The following measurements are for the core only and do not include any IOB registers or the Transmitter Elastic Buffer added in the example design Transmit Path Latency As measured from a data o...

Page 208: ...GMII until that data appears on txdata 7 0 on the MGT interface the latency through the core in the transmit direction is 4 clock periods of userclk2 Receive Path Latency As measured from a data octe...

Page 209: ...he target system has the maximum system margin required to perform across voltage temperature and process multiple chips variations Testing the system to determine the best DCM phase shift setting has...

Page 210: ...ional edge at a step size of two on more than one board refines the typical operational phase shift range Once the range is determined choose the average of the high and low working phase shift values...

Page 211: ...forms the opposite function it uses the Ordered Sets to detect the Ethernet frames and from them creates the GMII receive signals Cross reference Table D 1 with the remainder of this Appendix See IEEE...

Page 212: ...hat the encoding of Idle periods I2 is constructed from a couple of code groups the K28 5 character considered the even position and the D16 2 character considered the odd position In this example the...

Page 213: ...Engine this stream is transmitted out of the core either serially using the RocketIO transceiver or in parallel across the TBI In this example the assertion of the gmii_tx_en signal of the GMII occurs...

Page 214: ...up S is again replaced with a preamble byte However the first preamble byte of the original transmit GMII see Figure D 3 frame which was replaced with the D16 2 character to complete the Idle sequence...

Page 215: ...se Figure D 5 illustrates the translation of GMII encoding into the code group stream performed by the PCS Transmit Engine This stream is transmitted out of the core either serially using the RocketIO...

Page 216: ...is transmitted out of the core either serially using the RocketIO transceiver or in parallel across the TBI In response to the deassertion of gmii_tx_en an End of Packet code group T is immediately i...

Page 217: ...ocketIO transceiver or in parallel across the TBI and translation of this code group stream into the receiver GMII This is performed by the PCS Receive Engine Note that as defined in IEEE 802 3 figure...

Page 218: ...218 www xilinx com Ethernet 1000BASE X PCS PMA or SGMII v9 1 UG155 March 24 2008 Appendix D 1000BASE X State Machines R...

Page 219: ...lock tolerances 100 ppm there can be a maximum difference of one clock edge every 5000 clock periods of the nominal 125 MHz clock frequency This slight difference in clock frequency on either side of...

Page 220: ...is based across an asynchronous boundary Because there is a worst case scenario of one clock edge difference every 5000 clock periods the maximum number of clock cycles bytes that can exist in a sing...

Page 221: ...same Instead of the half full point there are configurable clock correction thresholds During the interframe gap clock correction will attempt to restore the occupancy to within these two thresholds...

Page 222: ...eption then there are 62 6 56 FIFO locations available before the buffer reaches the underflow mark Note that this analysis assumes the buffer is approximately at the half full level at the start of t...

Page 223: ...eep latency low Each FIFO word corresponds to a single character of data equivalent to a single byte of data following 8B10B decoding The shaded area of Figure E 3 represents the usable buffer availab...

Page 224: ...ons Idle Character Removal at 1Gbps 1000BASE X and SGMII The minimum number of clock cycles that may be presented to an Ethernet receiver according to the IEEE 802 3 specification is 64 bit times at a...

Page 225: ...bytes Because each byte at 100 Mbps is repeated ten times this corresponds to an Ethernet frame size of 20000 bytes the same size as the 1 Gbps case So in summary at 100Mbps for any frame size of 2000...

Page 226: ...core All frame sizes are provided in bytes Jumbo Frame Reception A jumbo frame is an Ethernet frame which is deliberately larger than the maximum sized Ethernet frame allowed in the IEEE 802 3 specifi...

Page 227: ...all 0s as a default If all 0s are read back the read was unsuccessful Check that the PHYAD field placed into the MDIO frame matches the value placed on the phyad 4 0 port of the core Problems with Da...

Page 228: ...nd see Problems with a High Bit Error Rate 2 Try disabling Auto Negotiation in both the core and the link partner and see if both devices report a valid link and are able to pass traffic If they do it...

Page 229: ...and to the RocketIO Problems with a High Bit Error Rate Symptoms The severity of a high bit error rate can vary and cause any of the following symptoms Failure to complete Auto Negotiation when Auto N...

Page 230: ...issues Place the RocketIO into parallel or serial loopback If the core exhibits correct operation in RocketIO serial loopback but not when loopback is performed via an optical cable it may indicate a...

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