VIPA SSM-BG41, Manual

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Application of interfaces without data handling blocks Manual BG41/BG42/BG43
4-86 Rev. 99/49
BIT 5 = 1:
indicates, that the building block has received data, which is to be found in the reception buffer. If
the corresponding channel also functions as the receiver, this bit should be cyclically polled, so that
the data can be read where necessary. Otherwise an overflow can occur in the reception buffer.
If bit 5 = 0, reading access is not allowed, as in this case the building block does not acknowledge
this. It also takes 20 µs before another character is made available in the reception channel.
Data register interface channel
If a channel is used for the operation of a DCF77 antenna module, information on the DCF77
system can be read on a continuous basis.
The bits of the corresponding periphery bytes have the following significance:
Fig. 4-15: Data register interface channel