VIPA SSM-BG41, Manual

Page: 201 / 286

Manual BG41/BG42/BG43 Software
Rev. 99/49 4-85
4.2.2 Interface channel
Status register interface channel
Fig. 4-14: status register interface channel
If the bits to be evaluated are set, the interfaces have the following status:
BIT 7 = 1:
indicates, that the transmission buffer of the respective channel is empty i.e. without further status
query, 256 bytes can be written in succession into the data channel. Once a byte has been entered,
the repeated access from the PLC to data channel is immediately possible. However, the building
block only acknowledges this access after 20 µs with READY. This time is required in order to
process the data in the building block. After that, all data in the transmission buffer is automatically
sent from the corresponding interface.
BIT 6 = 1:
indicates that the transmission buffer is ready. The bit should be queried before a single access. If
the transmission buffer is not ready, the building block does not acknowledge anything and it results
in an acknowledgement delay error (QVZ) in the PLC’s program.
Due to temporal reasons a buffer overflow can not be intercepted by
setting this bit. Control of the buffer allocation is carried by either the
standard software or by the user software.