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MVP3
SYSTEM BOARD
AWARD BIOS SETUP
4-21
PCI Dynamic Bursting
When Enabled, data transfers on the PCI bus, where possible, make use of the
high-performance PCI bust protocol, in which greater amounts of data are
transferred at a single command..
The choice: Enabled, Disabled.
PCI Master 0 WS Write
When Enabled, writes to the PCI bus are command with zero wait states.
The choice: Enabled, Disabled.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI specification
version 2.1.
The choice: Enabled, Disabled.
PCI Master Read Prefetch
This item allows you enable/disable the PCI Master Read Prefetch.
The choice: Enabled, Disabled.
PCI #2 Access #1 Retry
This item allows you enable/disable the PCI #2 Access #1 Retry.
The choice: Enabled, Disabled.
PCI Master 1 WS Write
This implements a single delay when writing to the PCI Bus. By default, two-wait
states are used by the system, allowing for greater stability.
The choice: Enabled, Disabled.
PCI Master 1 WS Read
This implements a single delay when reading to the PCI Bus. By default, two-wait
states are used by the system, allowing for greater stability.
The choice: Enabled, Disabled.