VIA Technologies MVP3, Operation Manual

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MVP3
SYSTEM BOARD
HARDWARE SETUP
3-14
CPU TYPE JP1~6, JP9~10 JP14~JP18 CPU TYPE JP1~6, JP9~10 JP14~JP18
75MHz x 2 V
CORE
= 2.9V 66MHz x 3 V
CORE
= 2.9V
Cyrix 1 2 1 2 Cyrix 1 2 1 2
/ IBM JP1 JP14 / IBM JP1 JP14
6x86MX JP2 JP15 6x86MX JP2 JP15
-PR200 JP3 JP16 -PR233 JP3 JP16
(75MHz JP4 JP17 (66MHz JP4 JP17
Bus) JP5 JP18 Bus) JP5 JP18
JP6 JP6
JP9 JP9
JP10 JP10
CPU TYPE JP1~6, JP9~10 JP14~JP18 CPU TYPE JP1~6, JP9~10 JP14~JP18
75MHz x 2.5 V
CORE
= 2.9V 83MHz x 2.5 V
CORE
=2.9V
Cyrix 1 2 1 2 Cyrix 1 2 1 2
/ IBM JP1 JP14 6x86 MII JP1 JP14
6x86MX JP2 JP15 -266 JP2 JP15
-PR233 JP3 JP16 / IBM JP3 JP16
(75MHz JP4 JP17 6x86MX JP4 JP17
Bus) JP5 JP18 -PR266 JP5 JP18
JP6 (83MHz JP6
JP9 Bus) JP9
JP10 JP10
CPU TYPE JP1~6, JP9~10 JP14~JP18 CPU TYPE JP1~6, JP9~10 JP14~JP18
66MHz x 3.5 V
CORE
= 2.9V 75MHz x 3 V
CORE
= 2.9V
Cyrix 1 2 1 2 Cyrix 1 2 1 2
6x86MII JP1 JP14 6x86MII JP1 JP14
-300 JP2 JP15 -300 JP2 JP15
/ IBM JP3 JP16 / IBM JP3 JP16
6x86MX JP4 JP17 6x86MX JP4 JP17
-PR300 JP5 JP18 -PR300 JP5 JP18
(66MHz JP6 (75MHz JP6
Bus) JP9 Bus) JP9
JP10 JP10
Note: Please select the correct FSB clock when using Cyrix and IDT CPU. Wrong setting
may cause problem to the PC system