MVP3
SYSTEM BOARD
AWARD BIOS SETUP
4-11
4.6
CHIPSET FEATURES SETUP
ROM PCI / ISA BIOS (2A5LEXXX)
CMOS SETUP UTILITY
CHIPSET FEATURES SETUP
Bank 0/1 DRAM Timing
:
SDRAM 10ns
OnChip USB
: Enabled
Bank 2/3 DRAM Timing
: FP/EDO 70ns
USB Keyboard Support
: Disabled
Bank 4/5 DRAM Timing
: FP/EDO 70ns
SDRAM Cycle Length
: 3
Auto Detect DIMM/PCI CLK : Enabled
DRAM Read Pipeline
: Enabled
Spread Spectrum
: Disabled
Cache Rd+CPU Wt Pipeline
: Enabled
Cache Timing
: Fast
Video BIOS Cacheable
: Enabled
System BIOS Cacheable
: Enabled
Memory Hole At 15Mb Addr. : Disabled
AGP Aperture Size
: 64M
ESC : Quit
áâßà
: Select Item
F1
: Help
PU/PD/+/- : Modify
F5
: Old Values (Shift)F2 : Color
F7
: Load Setup Defaults
Fig. 4-5 CHIPSET FEATURES SETUP screen.
WARNING :
The selection fields on this screen are provided for the professional
technician who can modify the Chipset features to meet some specific requirement. If
you do not have the related technical background, do not attempt to make any change
except the following items.
This section allows you to configure the system based on the specific features of the
installed chipset. This chipset manages bus speeds and access to system memory
resources, such as DRAM and the external cache. It also coordinates communications
between the conventional ISA bus and the PCI bus. It must be stated that these items
should never need to be altered. The default settings have been chosen because they
provide the best operating conditions for your system. The only time you might
consider making any changes would be if you discovered that data was being lost while
using your system.
