VL-486-4 Reference Manual
CIO Chip – 69
CIO Chip
Introduction
The CIO Counter/Timer and Parallel I/O device is a general-purpose peripheral circuit that
satisfies most counter/timer and parallel I/O needs encountered in system design, and is therefore
helpful in real-time situations and for interrupt control.
Note
The text in this section has been copied directly from the Zilog Technical Manual.
Several functions on the CIO chip are not implemented at the hardware level on
the VL-486-4 CPU card, and some functions are not supported by VersaLogic. The
table below describes these exceptions:
Non Supported Function
Notes
Hardware Interrupt Vectoring
Several conditions within the CIO chip can generate
interrupts. These interrupts are sent to the VL-486-4
interrupt controller on IRQ15 (via jumper V13[2-3]).
In DOS configuration, this causes an INT 77h
resulting in a dispatch through the interrupt vector at
0000:01DCh. To maintain IBM/AT interrupt
compatibility, CIO generated hardware interrupt
vectors are not implemented. Fortunately, the vector
can be read from the Current Interrupt Vector
register to help determine the source of the interrupt.
All actions associated with an interrupt acknowledge
cycle occur when an IP bit is cleared by writing to
one of the Command and Status registers.
A code example is provided on page 109 which
illustrates this process.
Handshaking Port Operation
This function is operational without restriction,
however it is not fully documented in this manual.
Please consult the Zilog Technical Manual if you are
interested in this feature.
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