Register Description
VL-486-4 Reference Manual
CIO Chip – 71
P
ORT
C
All bits on Port C can be used as parallel I/O lines or as Counter/Timer 3 signals.
Only the three bit path registers are needed: the Data Path Polarity register, the Data Direction
register, and the special I/O Control register.
C
OUNTER
/T
IMERS
The three counter/timers are all identical. Each is composed of a 16-bit down-counter, a 16-bit
Time Constant register (which holds the value loaded into the down-counter), a 16-bit Current
Counter register (used to read the contents of the down-counter), and 8-bit registers for control
and status (the Mode Specification and the C/T Command and Status registers).
Up to four signals are accessible on connectors J2 and J5 (counter input, gate input, trigger input,
and counter/timer output) can be used as dedicated external access lines for each counter/timer.
Three different counter/timer output duty cycles are available: pulse, one-shot, and square-wave.
The operation of the counter/timers can be programmed independently as either retriggerable or
non-retriggerable.
I
NTERRUPT
C
ONTROL
L
OGIC
There are five registers (the Master Interrupt Control register, the Current Vector register, and
the three Interrupt Vector registers) associated with the interrupt logic. In addition, each port and
Counter/Timer Command and Status register includes three bits associated with the interrupt
logic: Interrupt Pending (IP), Interrupt Under Service (IUS), and Interrupt Enable (IE).
Register Description
I
NTRODUCTION
This chapter provides brief description of the command, status and data registers contained in the
CIO. Each description includes the register address, the operation of the individual bits, and the
state of the register after a reset (hardware or software).
For simplicity, the descriptions assume that the data path polarity of each bit is programmed to
be non-inverting.
