Master Control Registers
VL-486-4 Reference Manual
CIO Chip – 75
Table 51: Master Interrupt Control Register Bit Assignments
Bit
Mnemonic
Description
D7
MIE
Master Interrupt Enable — Provides a method to disable all interrupts. MIE
also affects whether or not status is included when reading interrupt vectors.
MIE = 0
Inhibits the CIO from generating interrupts. Vector reads do
not include status.
MIE = 1
Allows interrupt logic to operate normally. Vector reads
always include status, independent of the state of the
corresponding Vector Includes Status (VIS) bit.
D6
DLC
Disable Lower Chain — Daisy chain (interrupt) controI bit. Since the daisy-
chain is not implemented on the VL-486-4 card, this bit has no effect.
DLC = 0
IEO operates normally.
DLC = 1
Interrupt Enable Out (IEO) output is forced Low, disabling
interrupts from all lower-priority devices on the daisy-chain.
D5
NV
No Vector — Inhibits hardware vector generation during interrupt
acknowledge cycle. Since CIO generated hardware interrupt vectors are not
implemented on the VL-486-4, this bit should be set to 1 for normal operation.
NV = 0
If NV is written with 0, the interrupt vector is output as usual.
NV = 1
Interrupt vector disabled during an Interrupt Acknowledge
cycle. This allows the vector to be provided by external
hardware. It has no effect on the setting of the Interrupt
Under Service (IUS) bit.
D4
PAVIS
Port A Vector Includes Status — Controls whether or not status information
is included in the Port A interrupt vector.
PAVIS = 0
The value returned from the Port A Interrupt Vector register
(CIOAIV) is constant. The data always reflects the value
written to the Port A Base Interrupt Vector register.
PAVIS = 1
The value returned from the Port A Interrupt Vector register
is variable. Vector is modified to include status, which
indicates the cause of the interrupt. The state of this bit has
no effect on the value returned when the Port A Interrupt
Vector is register is read. When reading the vector, the MIE
bit determines if status is included in the vector, (that is, no
status is included if MIE = 0). See page 106 for further
information.
D3
PBVIS
Port B Vector Includes Status — Controls whether or not status information
is included in the Port B interrupt vector. This bit operates the same way that
PAVIS does. See text above for details.
D2
CTVIS
Counter/Timer Vector Includes Status — Controls whether or not status
information is included in the Counter/Timer vector. This bit operates the same
way that PAVIS does. See text above for details.
D1
1
Reserved — This bit has no function. Always reads as 1.
D0
RESET
Reset — Resets the CIO chip.
RESET = 1
Places the CIO chip into a reset condition. Reads from all
other registers will return 0 and writes to other registers are
ignored. Refer to page 107 for further information.
RESET = 0
Normal operation
