Counter/Timer Operation
96 – CIO Chip
VL-486-4 Reference Manual
S
TARTING THE
C
OUNTER
/T
IMER
The countdown sequence is initiated when the counter/timer is triggered and the down-counter is
loaded with the contents of the Time Constant register. The down-counter is normally loaded on
the rising edge of the external trigger input, or by writing a 1 to the Trigger Command Bit (TCB)
of the Command and Status register. But, for Counter/Timer 2 only, triggering can occur on the
falling edge of Counter/Timer 1’s internal output if the counters are linked via the trigger input.
Also, Counter/Timer 3 can be triggered by the handshake logic when it is used with the Pulsed
Handshake.
The trigger functions as the logical OR of all the potential triggers. Since the trigger function is
an OR function, and since it is rising-edge sensitive, any input remaining in its active state will
mask off other trigger sources as it stays High.
Note
In order to ensure the loading of a Trigger Constant on a particular rising edge of
the clocking signal, sufficient setup time must be allowed—the trigger must occur
prior to the immediately preceding falling edge of the clocking signal. (The
clocking signal equals the count input if in Counter mode or PCLK/2 if in Timer
mode.)
Figure 10. Trigger OR-Function Diagram
Figure 11. Gate AND-Function Diagram
C
OUNTDOWN
S
EQUENCE
The rate at which the down-counter counts is determined by the mode of the counter/timer. In the
Timer mode (the External Count Enable [ECE] bit is 0), the down-counter is clocked internally
by a signal that is half the frequency of the PCLK input to the chip. In the Counter mode (ECE is
1), the down-counter is decremented on the rising edge of the counter/timer’s counter input.
Once the down-counter is loaded, the countdown sequence continues toward terminal count as
long as all of the counter/timers’ hardware and software gate inputs are High. The gate inputs
are: the Gate Command bit of the Counter/Timer Command and Status register, and the external
gate input if enabled in the External Gate Enable bit of the counter/timer Mode Specification
register. Also, for Counter/Timer 2 use only, the counter/timer output (inverted) can be used as a
gate if linked via the gate in the Counter/Timer Link Controls bits of the Master Configuration
Control register. If any of the gate inputs go Low (0), the countdown halts. It resumes when all
gate inputs are 1 again. The gate function does not affect the trigger function.
The gate functions as the logical AND of all the potential gates.
