VersaLogic VL-486-4 Reference Manual Download Page 73

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Register Summary

VL-486-4 Reference Manual

Register Descriptions – 61

LPT1 P

ARALLEL

ORT

Table 38: LPT1 Parallel Port Registers

Mnemonic

R/W

Address

Name

LPRD

03BCh

Line Printer Read Data Register

LPWD

03BCh

Line Printer Write Data Register

LPS

03BDh

Line Printer Status Register

LPRC

03BEh

Line Printer Read Control Register

LPWC

03BEh

Line Printer Write Control Register

HIPSET

EGISTERS

Table 39: 82C721 Configuration Registers

Mnemonic

R/W

Address

Name

CAR

R/W

03F0h

Configuration Access Register

CR0

R/W

03F1h

Configuration Register 0

CR1

R/W

03F1h

Configuration Register 1

CR2

R/W

03F1h

Configuration Register 2

CR3

R/W

03F1h

Configuration Register 3

Table 40: 82C836 Configuration Registers

Mnemonic

R/W

Address

Name

ICRI

0022h

Internal Register Index

ICRD

R/W

0023h

Internal Register Data

Summary of Contents for VL-486-4

Page 1: ...Reference Reference Reference Reference Manual Manual Manual Manual VL 486 4 Industrial CPU Card for the STD 32 Bus ...

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Page 3: ...VL 486 4 Industrial CPU Card for the STD 32 Bus TM M486 4 ...

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Page 5: ...y effort has been made to ensure this document is error free VersaLogic makes no representations or warranties with respect to this product and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose VersaLogic reserves the right to revise this product and associated documentation at any time without obligation to notify anyone of such changes PC 104 ...

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Page 7: ...pport 5 2 DOS Based Quick Start 7 Introduction 7 Installation 8 Activating the Battery 8 Jumper Locations 9 Card Installation 10 Monitor and Keyboard Installation 11 Cable Installation 12 CMOS RAM Setup 12 CMOS Setup Options 13 Main CMOS Setup Menu 13 Basic CMOS Configuration 13 Advanced CMOS Configuration 13 Reset CMOS to Last Known Values 13 Reset CMOS to Factory Defaults 14 Write to CMOS and Ex...

Page 8: ...34 CPU Interrupt Request Inputs 35 Interprocessor Communications Interrupt Configuration 37 Non maskable Interrupt Configuration 37 DMA Configuration 38 DMA Channel Allocation 39 Board Initialization 40 82C836 Initialization 41 82C721 Initialization 42 486SXLC Initialization 42 RAM Refresh Initialization 43 4 Installation 45 Introduction 45 Activating the Battery 45 Card Insertion and Extraction 4...

Page 9: ...pecial Control Register 65 Watchdog Timer Hold Off Register 66 Map and Paging Control Register 67 6 CIO Chip 69 Introduction 69 Features 70 Overview 70 I O Ports 70 Ports A and B 70 Port C 71 Counter Timers 71 Interrupt Control Logic 71 Register Description 71 Introduction 71 CIO Registers 72 Register Access 73 State 0 73 State 1 73 Master Control Registers 74 Master Interrupt Control Register 74 ...

Page 10: ...w 92 Pattern Recognition Logic Operation 92 Bit Port Operation 92 Bit Port Simple Operation 92 Bit Port Pattern Recognition Operation 93 Counter Timer Operation 94 Counter Timer Architecture 94 Counter Timer Sequence Of Events 95 Initializing the Counter Timer 95 Starting the Counter Timer 96 Countdown Sequence 96 Ending Condition 97 Counter Timer Output 98 Linked Sequence 98 Interrupt Operation 9...

Page 11: ...roller II Data Book Zilog Inc 408 370 8000 Z8036 Z CIO Z8536 CIO Counter Timer and Parallel I O Unit Technical Manual STD Manufacturers Group 408 723 5083 STD 32 Bus Specification and Designer s Guide Texas Instruments 214 917 1264 TI486SXLC2 Data Book Microsoft Press 800 677 7377 The Programmer s PC Sourcebook Addison Wesley 617 944 3700 The Undocumented PC ...

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Page 13: ...programmable registers on the CPU card Chapter 6 CIO Chip Appendix A Schematics shows the circuit diagrams on the CPU card Introduction The VL 486 4 CPU card features a 32 bit 50 MHz clock doubled 486SXLC microprocessor up to 4MB RAM up to 1MB Flash EEPROM or EPROM two COM ports one LPT port digital I O and Opto 22 interface and real time clock The card can be used as a DOS or non DOS computer in ...

Page 14: ...tput provides up to 1A at 5V typical The power supply line is protected by a self resetting circuit breaker COM PORTS The two on board COM ports are hardware and software compatible with the PC AT architecture Baud rates are programmable from 50 baud to 115K baud COM1 is a standard RS 232 interface COM2 can be jumpered for RS 232 RS 422 or RS 485 operation PARALLEL PORT The bi directional parallel...

Page 15: ...y Interrupt sources and destinations can be configured with jumper blocks Interrupt lines connect to on card sources STD Bus sources and to a user connector DMA CONTROLLERS The VL 486 4 has two DMA controllers which provide a total of eight DMA channels four 8 bit channels and four 16 bit channels One 8 bit or 16 bit channel jumper selectable is available for general purpose use through a front pl...

Page 16: ...O Opto 22 Interface 16 lines of bi directional TTL compatible I O with Rack Power output Data Lines Input high voltage 2 0V min 5 3V max Input low voltage 0 3V min 0 8V max Output low voltage 0 5V 3 2 ma Output high voltage 2 4V 250 µA Rack Power 5V 1A Max protected with self resettable polyfuse Floppy Disk Drive Interface None Hard Disk Drive Interface None Software provided to network CPU with d...

Page 17: ... Reference Manual Overview 5 Technical Support If you have problems that this manual can t help you solve contact VersaLogic for technical support at 1 800 824 3163 You can also reach VersaLogic by e mail at info versalogic com ...

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Page 19: ...em options available from VersaLogic for the 486 4 card the h and i options contain a bootable version of DOS The CMOS RAM information is shipped in its default condition and will need to be configured for your particular system The most convenient method of setting up this information is by using a keyboard and monitor requires addition of a video card however a method is available to use COM2 to...

Page 20: ... cage place the card on a grounded static free surface component side up Use an anti static foam pad if available but not the card wrapper Do not slide the card over any surface The card should also protected during shipment or storage with anti static foam or bubble wrap To prevent damage to the lithium battery do not use black conductive foam or metal foil Warning The lithium battery may explode...

Page 21: ...Jumper Locations VL 486 4 Reference Manual DOS Based Quick Start 9 Jumper Locations Note Jumpers and resistor packs shown in as shipped configuration Figure 1 VL 486 4 CPU Card Layout ...

Page 22: ...ved from the card cage only when the system power is off Caution To avoid damaging cards they must be oriented correctly usually with the card ejector toward the top of the card cage Refer to the card cage documentation for the correct way to insert STD Bus cards Cards in this system have no requirements as to position User cabling needs can dictate card positions The recommended card positions be...

Page 23: ...6 4 Reference Manual DOS Based Quick Start 11 Monitor and Keyboard Installation A VGA monitor and IBM AT compatible keyboard should be connected to the VL SVGA 1 card as shown Figure 2 Jumpers Connections for a VL SVGA 1 Using a VGA Monitor ...

Page 24: ... Speaker N A External 8Ω speaker CMOS RAM Setup The VL 486 4 CPU card uses battery backed non volatile CMOS RAM provided by the real time clock chip to store system configuration settings You can change these system settings with the Setup program accessed manually at system boot The configuration information is read by the CPU upon system reset The Setup program is permanently stored in ROM and c...

Page 25: ... This option goes to another menu which allows you to change the following Date Time Floppy Drive and Hard Drive types not applicable on the VL 486 4 Console VGA Card or Serial Port ADVANCED CMOS CONFIGURATION This option goes to another menu which allows you to change the following Memory Caching Boot Sequence not applicable on the VL 486 4 Floppy Disk Drive Reset not applicable on the VL 486 4 I...

Page 26: ...ce A C Seek Floppy at Boot Disabled Numlock State at Boot Disabled Display Hit Del Enabled System Configuration Box Enabled Wait for F1 on Error Disabled Memory Parity Check Disabled Memory Test Tick Enabled Test Above 1M Enabled System BIOS Shadow Disabled Video BIOS Shadow Disabled Typematic Programming Enabled Typematic Rate Delay 250 ms Typematic Rate 30 cps Permanent master defaults to VGA Ke...

Page 27: ...data Upon reset the CPU detects if the CMOS RAM is corrupted by analyzing the checksum If you wish to completely clear the contents of the CMOS RAM briefly move jumper V5 to position 1 2 top position then back to the position 2 3 lower position and reboot the system This process will load the factory default setup parameters into the CMOS RAM Warning Do not apply power to the CPU card with jumper ...

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Page 29: ...n completes the process by initializing the circuits within the chipset This chapter does not describe how to initialize the standard DOS peripheral devices such as the serial ports and disk drive interfaces Hardware Jumper Summary Hardware option configuration is accomplished by installing or removing jumper plugs In this chapter the term in is used to indicate an installed jumper and out is used...

Page 30: ...Hardware Jumper Summary 18 Configuration VL 486 4 Reference Manual JUMPER BLOCK LOCATIONS Note Jumpers and resistor packs shown in as shipped configuration Figure 5 Jumper Block Locations ...

Page 31: ...d to J4 pin 6 Out RS 232 mode Frees J4 pin 6 for CTS2 COM2 Out 29 V4 5 6 RS 232 422 485 Mode Selector In RS 422 485 mode Out RS 232 mode Out 29 V4 7 8 RS 422 485 Differential Line Driver Control In RS 485 mode Enables software control of the differential line driver Out RS 422 mode Permanently enables the differential line driver Out 29 V4 9 10 RS 422 485 Transmission Line Termination In Terminate...

Page 32: ...cts INTRQ1 from IRQ1 In 32 V10 1 2 Interrupt Configuration IRQ3 COM2 interconnect In Connects COM2 to IRQ3 Out Disconnects COM2 from IRQ3 In 32 V10 2 3 Interrupt Configuration IRQ3 Front Plane Interrupt 1 interconnect In Connects Front Plane Interrupt 1 J5 pin 9 to IRQ3 Out Disconnects FPI1 from IRQ3 Out 32 V11 1 2 Interrupt Configuration IRQ11 INTRQ2 interconnect In Connects STD Bus INTRQ2 P50 to...

Page 33: ...s the CPU initialization code and application code There are no configuration jumpers for the ROM sockets COMPATIBLE ROM DEVICES The following non exhaustive list of memory devices can be used in the ROM sockets All parts must be 200 ns or less Caution VersaLogic makes no representation of the suitability reliability or availability of any of the memory devices Table 5 Compatible ROM Flash Devices...

Page 34: ...llowing non exhaustive list of memory devices can be used All parts must be 70 ns or faster and must use 1024 refresh cycles Note The 1M x 16 RAM is available from VersaLogic as part number 9650 Caution VersaLogic makes no representation of the suitability reliability or availability of any of the following memory devices Table 7 Compatible RAM Devices Dynamic RAM 42 pin SOJ without Parity Brand P...

Page 35: ...utting the card in service To activate the battery move jumper V5 to position 2 3 bottom position as shown Jumper V5 1 2 top position can be briefly used to erase the contents of the CMOS RAM should it become necessary to do so Table 8 CMOS RAM Jumpers Jumper Block Description As Shipped V5 1 2 CMOS RAM Erase In Erases CMOS RAM and Real Time Clock contents Out Normal operation V5 2 3 must be in In...

Page 36: ... of the VL 486 4 is arranged as follows Page 7 of Flash 0 is the system BIOS and always appears from 0F0000h to 0FFFFFh Bits D3 D0 in the MPCR register select which Flash ROM page is mapped into the Flash Frame 0E0000h to 0EFFFFh See MPCR register description on page 72 for further information ...

Page 37: ... addresses listed above as X FF00h For example if your I O card is addressed at 38h the software should use FF38h as the I O port address USING 10 BIT I O CARDS I O cards which only decode 10 address bits A0 A9 will work properly with the VL 486 4 when addressed in the following I O ranges 100h 1EFh 200h 27Fh 300h 3AFh A card which does not decode IOEXP low will repeat every 1024 400h bytes throug...

Page 38: ...ess bits A0 A15 will work properly with the VL 486 4 when addressed in the following I O ranges 0100h 01EFh 0200h 027Fh 0300h 03AFh 0500h 07FFh 0900h 0BFFh 0D00h 0FFFh X100h X3FFh X500h X7FFh X900h XBFFh XD00h XFFFh Where X 1 2 3 4 5 6 7 8 9 A B C D E or F Use of the IOEXP signal is not supported in 16 bit address mode ...

Page 39: ...422 OPERATION For RS 422 operation jumper V4 should be jumpered as shown Note This configuration inserts a 100 Ohm line termination resistor in the circuit An equivalent resistor must exist at the opposite end of the cable to form a 50 Ohm balanced transmission line RS 485 OPERATION Removing V4 9 10 leaves the data circuit unterminated so that COM2 can be used as an intermediate station in an RS 4...

Page 40: ...nd to J4 pin 6 Out RS 232 mode Frees J4 pin 6 for CTS2 COM2 Out V4 5 6 RS 232 422 485 Mode Selector In RS 422 485 mode Out RS 232 mode Out V4 7 8 RS 422 485 Differential Line Driver Control In RS 485 mode Enables software control of the differential line driver Out RS 422 mode Permanently enables the differential line driver Out V4 9 10 RS 422 485 Transmission Line Termination In Terminates data c...

Page 41: ...in 49 is connected to 5 volts on the STD Bus through a 1 Amp self resetting polyfuse If the I O rack is powered by a separate external supply either a jumper from the I O rack or the V1 jumper must be removed Note The 5 volt power output from the VL 486 4 can be shorted to ground if the connector is not correctly oriented at either end of the interface cable The use of keys in the connectors or ve...

Page 42: ... CONFIGURATION Jumper blocks V2 and V8 are used to select the bus mastering mode Table 11 Multiprocessor Configuration Jumpers Jumper Block Description As Shipped V2 3 4 Multiprocessor Configuration In Dual master mode Uses BUSAK P41 for bus arbitration Out Permanent or temporary master mode Out V2 5 6 Multiprocessor Configuration In Dual master mode Uses BUSRQ P42 for bus arbitration Out Permanen...

Page 43: ...and respond to the STD Bus signals SYSRESET and PBRESET in different ways depending on the bus master mode Permanent Master The CPU is reset by pressing the on board push button and optionally by a low level on PBRESET arriving on the bus Permanent masters are responsible for driving the SYSRESET signal to reset temporary masters in the same card cage which are configured to react to SYSRESET To p...

Page 44: ... the VL 486 4 Each jumper block is used to select one of two interrupt sources and route it to the interrupt controller Wire wrap techniques can be used on V9 through V13 to route interrupt sources to the CPU s IRQ inputs if the factory provided jumpers do not provide suitable connections Note Jumpers shown in as shipped configuration Figure 7 Interrupt Circuit Diagram ...

Page 45: ...t In Connects COM2 to IRQ3 Out Disconnects COM2 from IRQ3 In V10 2 3 Interrupt Configuration IRQ3 Front Plane Interrupt 1 interconnect In Connects Front Plane Interrupt 1 J5 pin 9 to IRQ3 Out Disconnects FPI1 from IRQ3 Out V11 1 2 Interrupt Configuration IRQ11 INTRQ2 interconnect In Connects STD Bus INTRQ2 P50 to IRQ11 Out Disconnects STD Bus INTRQ2 from IRQ11 In V11 2 3 Interrupt Configuration IR...

Page 46: ... or Interprocessor Communications Interrupt IPC INTRQ is hardwired into IRQ9 It can also be jumpered to drive IRQ1 by inserting jumper V9 1 2 INTRQ can also be used to carry the Interprocessor Communications Interrupt IPC between multiple CPU s by inserting jumper V7 1 2 Activity on INTRQ will drive IRQ5 INTRQ1 INTRQ1 P37 Carries Keyboard interrupts from VL SVGA 1 to VL 486 4 INTRQ1 is general pur...

Page 47: ...rld IRQ1 09h Keyboard INTRQ1 DOS BIOS expects keyboard interrupts on this input Comes from STD Bus via INTRQ or INTRQ1 The interrupt jumper on the VL SVGA 1 must match IRQ2 0Ah Slave Interrupt Controller Hardwired Internal signal not available to the outside world IRQ3 0Bh COM2 COM2 DOS BIOS usually expects COM2 interrupts on this input Comes from the on board COM2 circuitry or via Front Plane con...

Page 48: ... available Non DOS users should mask this interrupt IRQ11 73h Unassigned INTRQ2 IRQ11 can receive interrupts from STD Bus INTRQ2 or from the Front Plane connector J5 FPI2 IRQ12 74h Unassigned INTRQ3 IRQ12 can receive interrupts from STD Bus INTRQ3 or from the Front Plane connector J5 FPI3 IRQ13 75h Math Coprocessor No Connection Internal signal not available to the outside world Non DOS users shou...

Page 49: ...Description As Shipped V7 1 2 IPC Configuration IPC INTRQ interconnect In Connects IPC signal to STD Bus INTRQ P44 Out Disconnects IPC from INTRQ Out V7 2 3 IPC Configuration IPC INTRQ4 interconnect In Connects IPC signal to STD Bus INTRQ4 P05 Out Disconnects IPC from INTRQ4 Out NON MASKABLE INTERRUPT CONFIGURATION Jumper V8 5 6 is used to connect the STD Bus NMIRQ P46 signal to the CPU NMI input ...

Page 50: ...select the data size for DMA transfers requested through the front plane interrupt connector J6 Table 17 DMA Configuration Jumpers Jumper Block Description As Shipped V3 DMA Configuration In DMA from connector J6 serviced by DMA Channel 7 16 Bit Out DMA from connector J6 serviced by DMA Channel 3 8 Bit Out ...

Page 51: ...general purpose use through a front plane DMA connector J6 The remaining channels are accessible only by software Table 18 DMA Channel Allocation DMA Channel Data Width Channel Allocation 0 8 Bit Not Used 1 8 Bit Not Used 2 8 Bit On Card Floppy 3 8 Bit General DMA via Front Plane Request J6 Pin 2 FPRQ Acknowledge J6 Pin 4 FPAK V3 OUT 4 16 Bit Not Used 5 16 Bit Not Used 6 16 Bit Not Used 7 16 Bit G...

Page 52: ... with the following features 16 Bit DMA transfers operate with one wait state 8 Bit DMA transfers operate with one wait state DRAM operates with zero wait states ROM active in UMB from 0F0000h to 0FFFFFh Hidden refresh enabled 640K 1M extended DRAM for 2M CPU card 640K 3M extended DRAM for 4M CPU card COM1 is located at I O address 3F8h COM2 is located at I O address 2F8h LPT1 is located at I O ad...

Page 53: ...cription 01h 00h 00h DMA Wait State Control Register 40h Version Register 41h 08h 08h Channel Environment Register 42h Reserved 43h Reserved 44h 01h 01h Peripheral Control Register 45h Miscellaneous Status Register 46h 01h 01h Power Management Register 47h Reserved 49h 00h 00h RAM Write Protect Register 4Ah 00h 00h Shadow RAM Enable Register 1 4Bh 00h 00h Shadow RAM Enable Register 2 4Ch 00h 00h S...

Page 54: ... Configuration Mode Output AAh to port 03F0h Table 20 Chips Technologies 82C721 Initialization Data Index Number Initialization Data Description 00h 9Bh Configuration Register 0 01h 15h Configuration Register 1 02h DCh Configuration Register 2 03h 00h Configuration Register 3 486SXLC INITIALIZATION Several registers in the 486SXLC microprocessor must be initialized for proper operation of the VL 4...

Page 55: ...8h 0Ch Register C8h C9h 07h Register C9h CBh 00h Register CBh CCh 00h Register CCh CEh 00h Register CEh CFh 00h Register CFh RAM REFRESH INITIALIZATION The DRAM refresh must be initialized by sending the data listed in table below directly to the ports indicated Table 22 Refresh Initialization Port Number Initialization Data Description 61h 04h Mask DRAM Parity Interrupt 43h 54h Refresh Timer Comm...

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Page 57: ...e card wrapper Do not slide the card over any surface The card should also be protected during shipment or storage with anti static foam or bubble wrap To prevent damage to the lithium battery do not use black conductive foam or metal foil Warning The lithium battery may explode if mistreated Do not recharge disassemble or dispose of in fire Dispose of used batteries promptly Activating the Batter...

Page 58: ... 32 card cage the left most slot position is designated as Slot X and is not bussed in parallel with the other slots Do not insert the CPU or any I O card into this slot it is reserved for a bus arbiter or a power supply card STD 32 BUS INSTALLATION GUIDELINES The VL 486 4 card complies with all STD 32 specifications If the CPU is used with other STD 32 compatible I O cards the highest performance...

Page 59: ...CPU card CONNECTOR FUNCTIONS Table 23 Connector Functions Connector Function J1 COM1 Serial Port Connector J2 Digital I O Connector J3 LPT1 Parallel Port Connector J4 COM2 Serial Port Connector J5 Counter Timer Digital I O and Interrupt Connector J6 DMA Connector L1 Speaker Connector STD STD 32 BUS Interface CONNECTOR LOCATIONS Figure 8 Connector Locations ...

Page 60: ...d Cable Assemblies Connector Mating Connector Cable Part Description Connects to J1 COM1 3M 3473 6610 9575 1 ft 10 pin IDC to DB 9P External equipment e g modem 9551 9 ft 10 pin IDC to DB 25S null modem DTE device e g host PC J2 DIGITAL I O 3M 3414 6634 9571 1 5 34 pin IDC to 34 pin IDC Opto 22 Interface Rack J3 LPT1 3M 3421 6620 9576 1 ft 20 pin IDC to DB 25S External printer J4 COM2 3M 3473 6610...

Page 61: ...ernal Connections VL 486 4 Reference Manual Installation 49 CABLE ASSEMBLY DIAGRAMS The following diagrams show how to construct the cables which attach to the external connectors Figure 9 Cable Assemblies ...

Page 62: ...etect In 2 DSR Data Set Ready In 3 RXD Receive Data In 4 RTS Request To Send Out 5 TXD Transmit Data Out 6 CTS Clear To Send In 7 DTR Data Terminal Ready Out 8 RI Ring Indicator In 9 Ground Ground 10 N C Table 26 J4 RS 422 485 Serial Port Connector Pinout RS 422 RS 485 J4 Pin Signal Name Description Direction Signal Name Description Direction 1 N C N C 2 N C N C 3 TD2 Transmit Data Positive Out TD...

Page 63: ...ount Input 28 Ground Ground 29 PB6 Port B Data 6 Counter Timer 1 Trigger Input 30 Ground Ground 31 PB7 Port B Data 7 Counter Timer 1 Gate Input 32 Ground Ground 33 Power 5V Rack Power 34 Ground Ground PA0 PA7 Port A Data Lines These TTL input output signals transfer information between the CIO Port A and external devices The signals can be configured as inputs outputs tri state or open drain PB0 P...

Page 64: ...gnal Name Centronics Signal Signal Direction 1 STB Strobe Out 2 AFX Auto feed Out 3 PD0 Data bit 1 In Out 4 PERR Printer error In 5 PD1 Data bit 2 In Out 6 INIT Reset Out 7 PD2 Data bit 3 In Out 8 SLIN Select input Out 9 PD3 Data bit 4 In Out 10 Ground Ground 11 PD4 Data bit 5 In Out 12 Ground Ground 13 PD5 Data bit 6 In Out 14 Ground Ground 15 PD6 Data bit 7 In Out 16 PBSY Port busy In 17 PD7 Dat...

Page 65: ...of parallel I O accessed through Port C FPI1 Front Plane Interrupt 1 This TTL input signal is used as a general purpose interrupt request input If jumper V10 2 3 is inserted a low level or high to low transition applied to the FPI1 pin will request an interrupt via IRQ3 In DOS configuration this will cause an INT 0Bh resulting in a dispatch through the interrupt vector at 000 002Ch FPI2 Front Plan...

Page 66: ...ng DMA channel 3 is performed FPRQ should be held low until FPAK makes a low to high transition FPAK Front Plane DMA Acknowledge A low level on this TTL output signal indicates that the DMA controller has accepted a DMA request on the FPRQ input signal and is preparing to transfer data When FPAK returns high FPRQ should be returned to the high state FPWR Front Plane DMA Write A low level on this T...

Page 67: ... 4 Reference Manual Installation 55 L1 SPEAKER CONNECTOR Connector L1 is provided for connecting an 8Ω speaker to the card Table 31 Speaker Connector Pinout L1 Pin Signal Name Function 1 Timer 2 Out Speaker drive 2 Ground Ground ...

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Page 69: ...r References on page v Information on the registers internal to the CPU chip can be found in the TI486SXLC2 data book Register Summary The tables in this section list all programmable registers on the VL 486 4 CPU card They are organized in the following groups Table 32 Programmable Registers Registers Page DMA 1 Controller 64 DMA 2 Controller 65 DMA Page 65 COM1 Serial Port 66 COM2 Serial Port 66...

Page 70: ...nt Word Count DMA2ADRA R W 0004h DMA Channel 2 Current Address DMA2CNTA R W 0005h DMA Channel 2 Current Word Count DMA3ADRA R W 0006h DMA Channel 3 Current Address DMA3CNTA R W 0007h DMA Channel 3 Current Word Count DMACSA R W 0008h DMA Command Status Register DMARQA R W 0009h DMA Request Register DMAMASKA R W 000Ah DMA Single Bit Mask Register DMAMODEA R W 000Bh DMA Mode Register DMACBPA R W 000C...

Page 71: ... Status Register DMARQB R W 00D2h DMA Request Register DMAMASKB R W 00D4h DMA Single Bit Mask Register DMAMODEB R W 00D6h DMA Mode Register DMACBPB R W 00D8h DMA Clear Byte Pointer DMAMCB R W 00DAh DMA Master Clear DMACMB R W 00DCh DMA Clear Mask Register DMAWAMB R W 00DEh DMA Write All Mask Register Bits DMAWAXB R W 00DFh DMA Write All Mask Register Bits X DIRECT MEMORY ACCESS PAGE REGISTERS Tabl...

Page 72: ...Modem Control Register A LSRA R 03FDh Line Status Register A MSRA R 03FEh Modem Status Register A SCRA R W 03FFh Scratchpad Register A COM2 SERIAL PORT Table 37 COM2 Serial Port Registers Mnemonic R W Address Name RBRB R 02F8h Receiver Buffer Register B THRB W 02F8h Transmit Holding Register B DLLB R W 02F8h Divisor Latch LSB B IERB R W 02F9h Interrupt Enable Register B DLMB R W 02F9h Divisor Latc...

Page 73: ...Printer Read Control Register LPWC W 03BEh Line Printer Write Control Register CHIPSET REGISTERS Table 39 82C721 Configuration Registers Mnemonic R W Address Name CAR R W 03F0h Configuration Access Register CR0 R W 03F1h Configuration Register 0 CR1 R W 03F1h Configuration Register 1 CR2 R W 03F1h Configuration Register 2 CR3 R W 03F1h Configuration Register 3 Table 40 82C836 Configuration Registe...

Page 74: ... W 03F7h Data Rate Register FDCFDR R 03F7h Fixed Disk Register IDE HARD DISK DRIVE CONTROLLER Table 42 IDE Hard Disk Drive Controller Registers Mnemonic R W Address Name IDEDR R W 01F0h Data Register IDEER R 01F1h Error Register IDEWP W 01F1h Write Precompensation Register IDESC R W 01F2h Sector Count Register IDESN R W 01F3h Sector Number Register IDECNL R W 01F4h Cylinder Number Register Low IDE...

Page 75: ...0020h In Service Register IRRA R 0020h Interrupt Request Register IPWA R 0020h Interrupt Poll Word IMRA R 0021h Interrupt Mask Register INTERRUPT CONTROLLER SLAVE Table 44 Slave Interrupt Controller Registers Mnemonic R W Address Name ICW1B W 00A0h Initialization Command Word 1 ICW2B W 00A1h Initialization Command Word 2 ICW3B W 00A1h Initialization Command Word 3 ICW4B W 00A1h Initialization Comm...

Page 76: ... Load Read TCW W 0043h Timer Control Word MISCELLANEOUS Table 46 Miscellaneous PC AT Style Registers Mnemonic R W Address Name CSP R W 0061h Control Status Port RTCIDX W 0070h Real Time Clock Index and NMI Mask RTCDP R W 0071h Real Time Clock Data Port CIO CHIP Table 47 CIO Registers Mnemonic R W Address Name CIOCONTROL R W 00E4h Control Port CIOPORTA R W 00E5h Port A Data Port CIOPORTB R W 00E6h ...

Page 77: ...block V7 configures the TIPC signal to be carried on the STD Bus signal INTRQ P44 As an alternative TIPC can be carried on the STD Bus signal INTRQ4 P05 An active low signal on this circuit generated locally by writing a 0 to this bit or received from the STD Bus requests an interrupt on IRQ5 In DOS configuration this causes an INT 0Dh resulting in a dispatch through the interrupt vector at 0000 0...

Page 78: ...card to reset the CPU if proper software execution fails or a hardware malfunction occurs The watchdog timer is enabled disabled by writing to bit D0 of SCR If the watchdog timer is enabled software must periodically refresh the watchdog timer at a rate faster than the timer is set to expire 250 ms Writing a 5Ah to WDHOLD resets the watchdog time out period preventing the CPU from being reset for ...

Page 79: ...ess to the on board ROM FPAGE 0 ROM Page Frame Disabled FPAGE 1 ROM Page Frame Enabled D4 Reserved This bit has no function Always reads as 0 D3 D0 RPG3 RPG0 ROM Page Select 3 0 Selects which 64K block of ROM will be mapped into the ROM page frame RPG3 RPG2 RPG1 RPG0 ROM Memory Range 0 0 0 0 00000h to 0FFFFh 0 0 0 1 10000h to 1FFFFh 0 0 1 0 20000h to 2FFFFh 0 0 1 1 30000h to 3FFFFh 0 1 0 0 40000h ...

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Page 81: ... chip can generate interrupts These interrupts are sent to the VL 486 4 interrupt controller on IRQ15 via jumper V13 2 3 In DOS configuration this causes an INT 77h resulting in a dispatch through the interrupt vector at 0000 01DCh To maintain IBM AT interrupt compatibility CIO generated hardware interrupt vectors are not implemented Fortunately the vector can be read from the Current Interrupt Ve...

Page 82: ...s two general purpose 8 bit ports which are linkable into one 16 bit port and one special purpose 4 bit port PORTS A AND B The two general purpose 8 bit I O ports Ports A and B are identical except that Port B can be programmed to provide external access to Counter Timers 1 and 2 Either port can be programmed to be a control port with the direction of each bit individually programmable Both ports ...

Page 83: ...s lines for each counter timer Three different counter timer output duty cycles are available pulse one shot and square wave The operation of the counter timers can be programmed independently as either retriggerable or non retriggerable INTERRUPT CONTROL LOGIC There are five registers the Master Interrupt Control register the Current Vector register and the three Interrupt Vector registers associ...

Page 84: ...h Counter Timer 3 Current Count LS Byte 96 CIOCT1TCM R W 16h Counter Timer 1 Time Constant MS Byte 95 CIOCT1TCL R W 17h Counter Timer 1 Time Constant LS Byte 95 CIOCT2TCM R W 18h Counter Timer 2 Time Constant MS Byte 95 CIOCT2TCL R W 19h Counter Timer 2 Time Constant LS Byte 95 CIOCT3TCM R W 1Ah Counter Timer 3 Time Constant MS Byte 95 CIOCT3TCL R W 1Bh Counter Timer 3 Time Constant LS Byte 95 CIO...

Page 85: ...the Index register The logic reverts back to state 0 Data read from the Control port 00E4h comes from the internal control register pointed to by the Index register The logic reverts back to state 0 For example to read the Current Vector register OUTPUT 00E4h 1Fh Write 1Fh to the Index register INPUT 00E4h Read the value of the Current Vector register In state 1 many internal operations are suspen...

Page 86: ...rt and counter timer enable bits port and counter timer link bits and the RESET bit MASTER INTERRUPT CONTROL REGISTER CIOMIC READ WRITE 00H D7 D6 D5 D4 D3 D2 D1 D0 MIE DLC NV PAVIS PBVIS CTVIS 1 RESET The Master Interrupt Control register contains the primary control bits for the interrupt control logic When the CIO chip is reset all bits in all device registers are forced to 0 except RESET which ...

Page 87: ...n the setting of the Interrupt Under Service IUS bit D4 PAVIS Port A Vector Includes Status Controls whether or not status information is included in the Port A interrupt vector PAVIS 0 The value returned from the Port A Interrupt Vector register CIOAIV is constant The data always reflects the value written to the Port A Base Interrupt Vector register PAVIS 1 The value returned from the Port A Int...

Page 88: ...from issuing an interrupt request its IP cannot be set however if IP was already set clearing PBE inhibits READY WAIT assertion holds all1 s catchers in a transparent condition and forces the Port B I O lines into a high impedance state PBE 1 Allows Port B to operate normally D6 CT1E Counter Timer 1 Enable Controls counter timer 1 CT1E 0 Counter Timer 1 is put into an initialized state its IP cann...

Page 89: ... the Port C I O lines into a high impedance state PCECT3E 1 Counter timer 3 and Port C function normally D3 PLC Port Link Control Unsupported PLC 0 Ports A and B operate as two independent 8 bit ports PLC 1 Unsupported D2 PAE Port A Enable This bit allows Port A to be configured initially without setting its IP erroneously or having its I O lines go low impedance until it is safe to do so PAE 0 In...

Page 90: ...tch Only Unsupported IMO 0 Normal operation IMO 1 Unsupported D2 D1 PMS1 PMS0 Pattern Mode Specification Bits These two bits define the mode of operation of the pattern of match logic PMS1 PMS0 Pattern Mode 0 0 Disable Pattern Match 0 1 AND Mode 1 0 OR Mode 1 1 OR Priority Encoded Vector mode The OR Priority Encoded Vector mode must not be specified for ports configured as bit ports with the Latch...

Page 91: ...t supported All bits must be remain in their reset state 0 PORT COMMAND AND STATUS REGISTERS CIOACS READ PARTIAL WRITE 08H CIOBCS READ PARTIAL WRITE 09H D7 D6 D5 D4 D3 D2 D1 D0 IUS ICB2 IE ICB1 IP ICB0 ERR ORE IRF PMF IOE Each of these registers contain the primary command and status bits for its port Other than the data bits themselves these are the bits most often accessed in normal port operati...

Page 92: ... using the coded ICB2 ICB0 bits D7 D5 Write ICB2 ICB0 Interrupt Command Bits These three bits control the port IP IUS and IE bits ICB2 ICB1 ICB0 Function 0 0 0 Null Code 0 0 1 Clear IP and IUS 0 1 0 Set IUS 0 1 1 Clear IUS 1 0 0 Set IP 1 0 1 Clear IP 1 1 0 Set IE 1 1 1 Clear IE D4 Read ERR Interrupt Error This status bit is automatically set to 1 along with IP when for a bit port with pattern matc...

Page 93: ... DP7 DP6 DP5 DP4 DP3 DP2 DP1 DP0 The Data Path Polarity registers each define whether the bits in its port are inverting or non inverting on a bit by bit basis Table 56 Register Bit Assignments Bit Mnemonic Description D7 D0 DP7 DP0 A 0 in a particular bit position of this register specifies the corresponding bit path of the port as non inverting that is a High level at the port pin is 1 If a bit ...

Page 94: ...function depends on the direction of data flow defined for the path Table 58 Register Bit Assignments Bit Mnemonic Description D7 D0 SC7 SC0 If a bit is an input bit a 1 in this register s corresponding bit position invokes a 1 s catcher A 1 s catcher functions automatically latching a 1 if its input goes to 1 It is cleared only by writing a 0 to the Input Data register A 1 s catcher is inserted i...

Page 95: ...EAD WRITE 2EH D7 D6 D5 D4 D3 D2 D1 D0 PT7 PT6 PT5 PT4 PT3 PT2 PT1 PT0 PATTERN MASK REGISTER CIOAPM READ WRITE 27H CIOBPM READ WRITE 2FH D7 D6 D5 D4 D3 D2 D1 D0 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 The pattern specified by the Pattern Definition registers is a logical not a physical specification this concept is important in understanding the interaction between the pattern match logic and the invert no...

Page 96: ...o directly accessible at I O Port 00E5h CIOPORTB READ WRITE 0EH also directly accessible at I O Port 00E6h D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Ports A and B each have a data path that is composed of three registers an Input Data register an Output Data register and a Buffer register Output data written to the data register is stored in the Output Data register Reading the data register...

Page 97: ...o the write protect mask bit enables writing to the corresponding bit in Port C Writing a 1 inhibits writing the corresponding bit in Port C Reading Port C always returns 1 s in the upper four bits Note A reset does not effect the contents of the data registers COUNTER TIMER CONTROL REGISTERS Each counter timer has a set of counter timer Control registers which perform several functions for the co...

Page 98: ... line will cause the down counter to be loaded To guarantee that the counter timer will be triggered on a particular rising edge of the clocking signal PCLK 2 or counter input the trigger rising edge must satisfy a setup time to the preceding falling edge of the clocking signal As in the external count input the bit of the port must be available for use by the counter timer and must be programmed ...

Page 99: ... READ PARTIAL WRITE 0CH D7 D6 D5 D4 D3 D2 D1 D0 IUS ICB2 IEICB1 IP ICB0 ERR RCC GCB TCB CIP Each Counter Timer Command and Status register contains the primary command and status bits for its counter timer and in most cases will be the register most often accessed A reset forces all bits to 0 The detailed bit descriptions will discuss whether or not a bit can be read or written ...

Page 100: ...r timer requires servicing It is automatically set to1 each time the counter timer reaches its terminal count or by the CPU command If IE is also 1 and no higher priority interrupts are under service then the INT line is pulled Low to request an interrupt This bit is read write It is changed by writing to this register using the coded ICB2 ICB0 bits D7 D5 Write ICB2 ICB0 Interrupt Command Bits The...

Page 101: ...unt In Progress CIP is a status bit that indicates if a countdown sequence is on progress It is automatically set to 1 when the counter timer is triggered and the down counter is loaded with the time constant value It is automatically reset to 0 when the down counter reaches a count of 0 The state of the gate inputs internal and external has no effect on this bit CIP is read only COUNTER TIMER TIM...

Page 102: ...t the value is frozen Writes to the CCR are ignored A reset forces the CCR to follow the down counter neither are forced to a specific value Interrupt Related Registers These registers contain the interrupt vectors output during Interrupt Acknowledge sequences Three vector registers are provided one for Port A one for Port B and one shared by the three counter timers Another register is provided w...

Page 103: ...the highest priority counter timer with an interrupt pending also has its ERR flag set The CPU must poll the Command and Status registers to determine which counter timer has its ERR flag set CURRENT VECTOR REGISTER CIOCV READ 1FH D7 D6 D5 D4 D3 D2 D1 D0 CV7 CV6 CV5 CV4 CV3 CV2 CV1 CV0 When the Current Vector register is read it returns the interrupt vector that would have been output by the devic...

Page 104: ... to 1 transition 1 to 0 transition or any transition Individual bits can be masked off Three modes of pattern recognition operation are supported AND OR and OR Priority Encoded Vector OR PEV A pattern match is defined as the simultaneous satisfaction of all non masked bit specifications in the AND mode or the satisfaction of any non masked bit specifications in either the OR or OR PEV modes The pa...

Page 105: ...o detect a user specified pattern and to generate an interrupt request when the pattern is detected Pattern recognition may be performed on all bits including those used as I O for the counter timers For input bits the input to the pattern recognition logic reflects the value on the pins through the invert non invert logic in all cases except for inputs with 1 s catchers In this case the outputs o...

Page 106: ... to match transition is not required the source of the interrupt must be cleared before IP is cleared or else a second interrupt is generated No programmer error detection is performed in this mode and the Interrupt on Error bit should be 0 One application of the OR PEV pattern match mode is to use the CIO as a Programmable Interrupt Controller PIC Counter Timer Operation COUNTER TIMER ARCHITECTUR...

Page 107: ...d by writing the desired value to the Time Constant register The Time Constant register is accessed as two 8 bit registers The registers are readable as well as writeable and can be accessed in any order A 0 in the Time Constant register specifies a Time Constant of 65 536 Third if external access is going to be provided the port to be used must be programmed as a bit port and the necessary bits m...

Page 108: ...gnal The clocking signal equals the count input if in Counter mode or PCLK 2 if in Timer mode Figure 10 Trigger OR Function Diagram Figure 11 Gate AND Function Diagram COUNTDOWN SEQUENCE The rate at which the down counter counts is determined by the mode of the counter timer In the Timer mode the External Count Enable ECE bit is 0 the down counter is clocked internally by a signal that is half the...

Page 109: ...ime However reading the register is asynchronous to the counter s counting and the value returned can be guaranteed as valid only if the counter is stopped The down counter can be read reliably while it is counting by first writing a 1 to the Read Counter Control RCC bit in the counter timer s Command and Status register This freezes the value in the Current Count register until a read of the leas...

Page 110: ...ount is detected on the down counter s clocking edge the output goes High and the time constant value is reloaded On the clocking edge when both the down counter and the output are 1 s the output is forced Low LINKED SEQUENCE Counter Timers 1 and 2 can be linked internally in three different ways Counter Timer 1 s output inverted can be used as Counter Timer 2 s trigger gate or counter input When ...

Page 111: ...hree bits for the control and status of the interrupt logic an Interrupt Pending IP bit an Interrupt Under Service IUS bit and an Interrupt Enable IE bit IP is automatically set when an event requiring CPU intervention occurs The setting of IP results in an Interrupt Request on IRQ15 via jumper block V13 1 2 IP can also be set by a command This is useful when debugging interrupt handler software T...

Page 112: ...trolled independently When MIE 1 reading the base vector register always includes status independent of the state of the VIS bit All the information obtained by the vector including status can thus be obtained with one additional instruction when VIS is set to 0 When MIE 0 reading the vector register returns the unmodified base vector so that it can be verified Another register the Current Vector ...

Page 113: ...the associated interrupt needs to be cleared CIO Initialization INTRODUCTION The CIO is reset by writing a 1 to the Reset bit D0 in the Master Interrupt Control register RESET disables all functions except a read or write to the Reset bit In the reset state the pointer always points to the Master Interrupt Control register Writes to all other bits are ignored and all reads return 01h In this state...

Page 114: ...e operates in the same way and until set to 1 the handshake logic for Ports A and B is forced into an idle state The Counter Timer Enables when set to 0 terminate any countdown sequence in progress inhibit the counter timer from being triggered and force the counter output to 0 While the enable is 0 the Read Counter Control RCC bit in the Counter Timer Command and Status register is forced to 0 In...

Page 115: ...t E7 23h and E7 00h returned value x n in_val1 printf Make Port B bits inputs n outportb 0xE7 0x2B Set all Port B bits to input outportb 0xE7 0xFF outportb 0xE7 0x2B Test if values are written to Z8536 in_val1 inportb 0xE7 printf Output E7 2Bh and E7 FFh returned value x n in_val1 printf Enable ports A B C n outportb 0xE7 0x01 Enbale ports A B C outportb 0xE7 0x94 outportb 0xE7 0x01 Test if values...

Page 116: ...rtb 0xE7 0x09 Test if values are written to Z8536 in_val1 inportb 0xE7 printf Output E7 09h and E7 C0h returned value x n in_val1 Set value for Int vector register printf Write Port B Int vector register n outportb 0xE7 0x03 outportb 0xE7 0xAA outportb 0xE7 0x03 Test if values are written to Z8536 in_val1 inportb 0xE7 printf Output E7 03h and E7 AAh returned value x n in_val1 Set Master Interrupt ...

Page 117: ...Programming VL 486 4 Reference Manual CIO Chip 105 outportb 0xE6 0x55 in_val1 0x00FF inportb 0xE5 printf Output E6 55h Read in from E5 x n in_val1 ...

Page 118: ...ut E7 09h returned value x n in_val1 To clear IP bit write A0h to indexed register 09h printf Write Port B Command and Status register clear IP n outportb 0xE7 0x09 outportb 0xE7 0xA0 outportb 0xE7 0x09 Test if values are written to Z8536 in_val1 inportb 0xE7 printf Output E7 09h and E7 A0h returned value x n in_val1 Current vector register should be FF again printf Check value of Current Vector R...

Page 119: ...RP19F 1 2 RP15A 1 3 RP15B 1 4 RP15C 1 5 RP15D 1 6 RP15E 1 7 RP15F 1 5 RP17D 1 6 RP17E 1 7 RP17F 1 8 RP17G 1 4 RP17C P5 P7 P9 P11 P13 P15 P17 P19 P21 P23 P25 P27 P29 P31 P33 P35 R12 1 5 RP19D 1 2 RP17A 1 3 RP17B P37 P39 P45 E15 P47 P49 P51 P41 STD32P E13 E13 E15 E15 E17 E17 E19 E19 E21 E21 E23 E23 E25 E25 E27 E27 E29 E29 E31 E31 E33 E33 E35 E35 E37 E37 E39 E39 E41 E41 E43 E43 E45 E45 E47 E47 E49 E4...

Page 120: ... E16 GP0 DRQx BEN IORQ MEMRQ STAT0 STAT1 BEN ALE BEN DAKx DRQx STD BUS BHE OE 1 A0 47 A1 46 A2 44 A3 43 Y0 2 Y1 3 Y2 5 Y3 6 U19A CT16244 OE 48 A0 41 A1 40 A2 38 A3 37 Y0 8 Y1 9 Y2 11 Y3 12 U19B CT16244 OE 48 A0 41 A1 40 A2 38 A3 37 Y0 8 Y1 9 Y2 11 Y3 12 U22B CT16240 5 RP2D R44 P29 P27 P25 P23 P21 P19 P32 P31 P36 P35 P49 P47 PM LA 1 23 P41 BRQ A0 A1 A2 A3 A4 A5 A0 A1 A2 A3 A4 A5 BEN RD WR PM RESET ...

Page 121: ... XIWR XMWR XMRD XI16 XRDY R11 R42 R32 R40 R41 6 RP5E 7 RP5F 2 RP7A 3 RP7B XIRD XD 0 15 RDY MA4 MA5 MA6 MA7 MA8 MA9 PARL PARH XIRD XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7 XD8 XD9 XD10 XD11 XD12 XD13 XD14 XD15 RDY MA2 M20 M23 MA5 MA6 MA7 MA8 M28 MA3 MA9 MA4 MA3 MA4 1Mx16 DRAM 256Kx16 DRAM R21 R19 R22 R20 R16 R23 MA2 M20 M23 MA5 MA6 MA7 MA8 M28 MA3 M28 M23 M20 M28 M23 M20 CE 22 RD 24 A18 1 WR 31 A17 30 A16 2...

Page 122: ... XD1 XD2 XD3 XD4 3 RP5B C18 C22 C21 C23 C1 C17 C19 DI1 7 DO1 8 T1 2 R1 9 T2 3 R2 4 T3 1 R3 27 R4 23 R5 18 DI2 6 DO2 5 DI3 20 DO3 26 DO4 22 DO5 19 C1 12 C1 14 C2 15 C2 16 EN 24 SD 25 V 17 V 13 NC1 21 NC2 28 U2 211 1 3 5 2 4 6 7 9 8 10 V4 RI1 DCD1 RI2 DSR2 RTS2 CTS2 DCD2 TXD2 RXD2 232 485 232 CTS2 232 422 422 COM2 C34 1 2 L1 D1 LED5V R1 1 3 5 7 9 2 4 6 8 10 J4 LED SPK DCD2 DSR2 RTS2 CTS2 RI2 DTR2 TX...

Page 123: ...Control Registers 64 Description 2 External Connector J5 53 Interrupts 35 Digital I O External Connector J2 51 External Connector J5 53 Direct Memory Access Channel 1 Control Registers 58 Channel 2 Control Registers 59 Channel Allocation 39 Configuration 38 Description 3 External Connector J6 54 Page Control Registers 59 DMA See Direct Memory Access Dynamic Bus Sizing 46 Electrostatic Discharge 8 ...

Page 124: ...s 35 Map and Paging Control Register 67 Memory Description 2 Mapping 24 Memory Map Control Register MPCR 67 Multiprocessing 34 Bus Arbiter 30 Configuration 30 Determining which type 65 Dual Master 30 Permanent Master 30 Reset Signals 31 Resistor Packs 31 Slot X 30 Temporary Master 30 Non Maskable Interrupt Interrupts 35 OPTO 22 29 Description 2 External Connector J2 51 Parallel Port See LPT1 Power...

Page 125: ...STD 32 Designer s Guide vii SVGA Card Installation 10 Card Placement 46 Installation 11 Interrupts 35 Termination 27 Timers See Counter Timers Transmission Line 27 VGA See SVGA Video Adapter See SVGA Watch Dog Timer Description 3 Watchdog Enable Disable 65 Hold Off 66 Z8036 See CIO ...

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