Bit Path Definition Registers
VL-486-4 Reference Manual
CIO Chip – 81
Bit Path Definition Registers
The Bit Path Definition registers are used to specify the details of each bit path of each port.
They define:
•
whether a bit path in inverting or non-inverting
•
if an output is normal or open-drain
•
if a bit port input has a 1's catcher inserted in its path
•
which direction the data is flowing for each bit of a bit port.
Each port has a set of these registers. The four most significant bits of each register do not exist
in the registers associated with Port C (writes are ignored, reads return 1s).
D
ATA
P
ATH
P
OLARITY
R
EGISTERS
CIOADPP (READ/WRITE) 22H
CIOBDPP (READ/WRITE) 2AH
CIOCDPP (READ/WRITE) 05H
D7
D6
D5
D4
D3
D2
D1
D0
DP7
DP6
DP5
DP4
DP3
DP2
DP1
DP0
The Data Path Polarity registers each define whether the bits in its port are inverting or non-
inverting on a bit-by-bit basis.
Table 56: Register Bit Assignments
Bit
Mnemonic
Description
D7-D0
DP7-DP0
A 0 in a particular bit position of this register specifies the corresponding bit
path of the port as non-inverting (that is, a High level at the port pin is 1). If a
bit in this register is written with 1, the data path is programmed inverting (that
is, a Low level at the pin is 1). A reset clears all bits to 0 (the port is non-
inverting). The bits are read/write. Only the four LSB's of Port C are affected.
D
ATA
D
IRECTION
R
EGISTERS
CIOADD (READ/WRITE) 23H
CIOBDD (READ/WRITE) 2BH
CIOCDD (READ/WRITE) 06H
D7
D6
D5
D4
D3
D2
D1
D0
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
Each of the Data Direction registers define the direction of data flow for the individual bits of its
port if configured as a bit port.
