Interrupt Related Registers
VL-486-4 Reference Manual
CIO Chip – 91
The Interrupt Vector register is a read/write register. When read, the value returned always
includes the status if MIE = 1 (whether or not the associated Vector Includes Status bit is 1). If
MIE = 0, the unmodified vector is returned independent of the state of the VIS bit. A reset does
not affect the Interrupt Vector register.
Table 62: Interrupt Vector Encoding if Vector Includes Status
Port Vector Status
OR-Priority Encoded
Vector Mode
All Other Modes
Counter/Timer Status
D3 D2 D1
x
x
x
Number of highest
priority bit with a match.
D3 D2 D1
ORE
IRF
PMF
Normal
0
0
0
Error*
D2 D1
0
0
Counter/Timer 3
0
1
Counter/Timer 2
1
0
Counter/Timer 1
1
1
Error
* The error status indicates that the highest-priority counter/timer with an interrupt pending also
has its ERR flag set. The CPU must poll the Command and Status registers to determine which
counter/timer has its ERR flag set.
C
URRENT
V
ECTOR
R
EGISTER
CIOCV (READ) 1FH
D7
D6
D5
D4
D3
D2
D1
D0
CV7
CV6
CV5
CV4
CV3
CV2
CV1
CV0
When the Current Vector register is read, it returns the interrupt vector that would have been
output by the device during an Interrupt Acknowledge cycle if its IEI input had been High. The
vector returned corresponds to the highest priority IP independent of the IUS. The order of
priority (highest to lowest) is: Counter/Timer 3, Port A, Counter/Timer 2, Port B, Counter/Timer
1. If no enabled interrupts are pending, a pattern of all 1’s is output. This is useful in a polled
environment or when CPU does not read vectors. This register is a read-only register. Since a
reset disables all interrupts, reading the Current Vector register after a reset will return all 1s.
