Master Control Registers
78 – CIO Chip
VL-486-4 Reference Manual
P
ORT
M
ODE
S
PECIFICATION
R
EGISTER
CIOBMS (READ/WRITE) 20H
CIOAMS (READ/WRITE) 28H
D7
D6
D5
D4
D3
D2
D1
D0
PTS1
PTS0
ITB
SB
IMO
PMS1
PMS0
LPM/DTE
Each port Mode Specification register contains the bits that define the operating mode of its port
and specify the operation of pattern match logic of the port. A reset forces all bits to 0.
Table 54: Port Mode Specification Register Bit Assignments
Bit
Mnemonic
Description
D7-D6
PTS1-PTS0
Port Type Selects — Unsupported.
PTS1
PTS0
Port Types
0
0
Bit Port (no handshake)
0
1
Unsupported
1
0
Unsupported
1
1
Unsupported
D5
ITB
Interrupt on Two Bytes — Unsupported.
ITB = 0
Normal operation.
ITB = 1
Unsupported
D4
SB
Single Buffer — Unsupported.
SB = 0
Normal operation
SB = 1
Unsupported
D3
IMO
Interrupt on Match Only — Unsupported.
IMO = 0
Normal operation
IMO = 1
Unsupported
D2-D1
PMS1-PMS0
Pattern Mode Specification Bits — These two bits define the mode of
operation of the pattern of match logic.
PMS1
PMS0
Pattern Mode
0
0
Disable Pattern Match
0
1
AND Mode
1
0
OR Mode
1
1
OR-Priority Encoded Vector mode.
The OR-Priority Encoded Vector mode must not be specified for ports
configured as bit ports with the Latch on Pattern Match (LPM) bit set to 1 or for
ports with handshake.
D0
LPM/DTE
Latch On Pattern Match/Deskew Timer Enable — This bit is a dual-function
bit. The LPM function is active when the port is specified in bit mode. It must
be cleared to 0 for input ports with handshake or for bit ports whose pattern
match logic is in the OR-Priority Encoded Vector mode.
LPM = 0
Pattern matches are still detected, but the data read back
from the port follows the port pins.
LPM = 1
Causes the port to latch the input data present at the port
when a pattern match is detected.
DTE = 0
Not supported.
DTE = 1
Not supported.
