Register Summary
VL-486-4 Reference Manual
Register Descriptions – 59
D
IRECT
M
EMORY
A
CCESS
— C
HANNEL
2
Table 34: DMA 2 Controller Registers
Mnemonic
R/W
Address
Name
DMA0ADRB
R/W
00C0h
DMA Channel 0 Current Address
DMA0CNTB
R/W
00C2h
DMA Channel 0 Current Word Count
DMA1ADRB
R/W
00C4h
DMA Channel 1 Current Address
DMA1CNTB
R/W
00C6h
DMA Channel 1 Current Word Count
DMA2ADRB
R/W
00C8h
DMA Channel 2 Current Address
DMA2CNTB
R/W
00CAh
DMA Channel 2 Current Word Count
DMA3ADRB
R/W
00CCh
DMA Channel 3 Current Address
DMA3CNTB
R/W
00CEh
DMA Channel 3 Current Word Count
DMACSB
R/W
00D0h
DMA Command/Status Register
DMARQB
R/W
00D2h
DMA Request Register
DMAMASKB
R/W
00D4h
DMA Single Bit Mask Register
DMAMODEB
R/W
00D6h
DMA Mode Register
DMACBPB
R/W
00D8h
DMA Clear Byte Pointer
DMAMCB
R/W
00DAh
DMA Master Clear
DMACMB
R/W
00DCh
DMA Clear Mask Register
DMAWAMB
R/W
00DEh
DMA Write All Mask Register Bits
DMAWAXB
R/W
00DFh
DMA Write All Mask Register Bits X
D
IRECT
M
EMORY
A
CCESS
— P
AGE
R
EGISTERS
Table 35: DMA Page Registers
Mnemonic
R/W
Address
Name
DMA2PG
W
0081h
DMA Channel 2 Page Register
DMA3PG
W
0082h
DMA Channel 3 Page Register
DMA1PG
W
0083h
DMA Channel 1 Page Register
DMA0PG
W
0087h
DMA Channel 0 Page Register
DMA6PG
W
0089h
DMA Channel 6 Page Register
DMA7PG
W
008Ah
DMA Channel 7 Page Register
DMA5PG
W
008Bh
DMA Channel 5 Page Register
RAPREG
W
008Fh
Refresh Address Page Register
