I/O Port Operation
VL-486-4 Reference Manual
CIO Chip – 93
The Data Path Polarity register provides the capability of inverting the data path. A 1 specifies
inverting, and a 0 specifies non-inverting. All discussions of the port operations assume that the
path is programmed non-inverting.
The value returned when reading an input bit reflects the state of the input just prior to the read.
A 1’s catcher can be inserted into the input data path by programming a 1 to the corresponding
bit position of the port’s Special I/O Control register. When a 1 is detected at the 1’s catcher
input, its output is automatically set to 1 until is it cleared by software. The 1’s catcher is cleared
by writing a 0 to the corresponding bit in the data register. In all other cases, attempted writes to
input ports are ignored. The 1’s catcher is level-sensitive. If the input is still a one when it is
cleared, the output will again be set to 1. Also, the input to the 1’s catcher follows the invert/non-
invert logic. If the bit is programmed inverting, a low voltage level at the pin will cause the 1’s
catcher output to go to a 1.
When Ports A and B include output bits, reading the data register returns the value being output.
Reads of Port C returns the state of the pins. Outputs can be specified as open-drain by writing a
1 to the corresponding bit of the port’s Special I/O Control register. Port C has the additional
feature of bit-addressable writes. When writing to Port C, the four most-significant bits are used
as a write protect mask for the least-significant bits (0-4, 1-5, 2-6, 3-7). With this feature, any
combination of bits can be set or cleared (while other bits remain undisturbed), without first
reading the register.
B
IT
P
ORT
P
ATTERN
-R
ECOGNITION
O
PERATION
Ports A and B contain pattern-recognition logic, which enables the port to detect a user-specified
pattern and to generate an interrupt request when the pattern is detected. Pattern-recognition may
be performed on all bits, including those used as I/O for the counter/timers. For input bits, the
input to the pattern-recognition logic reflects the value on the pins (through the invert/non-invert
logic) in all cases except for inputs with 1’s catchers. In this case, the outputs of the 1’s catcher
is used. For output bits, this is the value being output before the invert/non-invert logic is used.
When operating in the AND or OR mode, the transition from a no-match to a match state causes
the interrupt. In the OR mode, if a second match occurs before the first match goes away, it does
not cause a second interrupt. Bit ports specified in the OR-PEV mode generate interrupts as long
as a match state exists. A transition from a no-match to a match state is not required. Since a
match condition only lasts a short time when transition patterns are specified, care must be
taken—no more than one bit should be programmed with a transition match specifications in a
port operating in the AND mode.
The pattern-recognition logic of bit ports operates in two basic modes: Transparent and Latched.
When the Latch on Pattern Match (LPM) bit is set to 0 (Transparent mode), the interrupt
indicates that a specified pattern has occurred, but a read of the data register does not necessarily
indicate the state of the port at the time interrupt was generated. In the Latched mode (LPM = 1),
the state of all the port inputs at the time the match was detected is latched in the Buffer register
and held until IP is cleared. In all cases, the Pattern Match Flag (PMF) in the port’s Command
and Status register indicates the state of the port at the time PMF is read. Only Transparent mode
(LPM = 0) is supported when OR-PEV is specified. In all modes, the port’s IP bit is set and an
interrupt generated (if enabled) when the pattern match is detected. The IP can only be cleared
by a command to the Port Command and Status register.
