INST ALLA TIO N
4 - 1 3
Refer to Tab
l
e 4-1 0 and connect the ana
l
og
i
nputs to J 9 (9-p
i
n D-connector) on the
rear pane
l
of the 7 2 0 0 A C U.
TAB
L
E 4-10
ANA
L
OG
I
N
P
UT CONNECT
I
ONS
J9
DES
I
GNAT
I
ON
FUNCT
I
ON
1
GND
S
i
g Ground
2
A D 1 +
Channe
l
1( + ) *
3
A D 1 GND
Channe
l
1 (GND)
4
A D 2-
Channe
l
2(-) *
5
SPARE
No Connect
i
on
6
GND
S
i
g Ground
7
A D 1-
Channe
l
1(-) *
8
A D 2 +
Channe
l
2( + ) *
9
A D 2 GND
Channe
l
2 (GND)
* Standard connect
i
on procedure.
4.3.6.1 A/D C
a
r
d C
a
li
b
r
a
t
i
on
A ca
li
brat
i
on procedure
i
s norma
ll
y performed at the factory as part of the product
conf
i
gurat
i
on, therefore a f
i
e
l
d ca
li
brat
i
on
i
s on
l
y performed
i
f operat
i
ona
l
prob
l
ems
due to dr
i
ft are encountered at a
l
ater date, or
i
f d
i
fferent v
i
deo rece
i
vers are used
i
n the A G C mode. Shou
l
d f
i
e
l
d ca
li
brat
i
on be necessary, refer to A ppend
i
x D for the
ca
li
brat
i
on procedure.
The A /D converter daughter card
i
s used to convert ana
l
og D C vo
l
tage
l
eve
l
s
represent
i
ng track
i
ng s
i
gna
l
l
eve
l
s
i
nto a d
i
g
i
ta
l
format su
i
tab
l
e for the 7 2 0 0 A C U
process
i
ng rout
i
nes. It has t w o
i
ndependent converter channe
l
s, each of w h
i
ch has
the capab
ili
ty of convert
i
ng
li
near track
i
ng rece
i
ver vo
l
tage
l
eve
l
s or v
i
deo A G C
vo
l
tage
l
eve
l
s
i
nto a d
i
g
i
ta
l
format. Refer to eng
i
neer
i
ng dra w
i
ngs Sect
i
on 8 for a
schemat
i
c and p
i
ctor
i
a
l
v
i
e w of the fo
ll
o w
i
ng d
i
scuss
i
on.
S
i
te des
i
gnators
i
n parentheses
i
nd
i
cate the channe
l
2 s
i
gna
l
path. The
i
nput s
i
gna
l
i
s coup
l
ed
i
nto the board through J 9R. From here the s
i
gna
l
s are routed to JP1
(JP2) w h
i
ch e
i
ther coup
l
es the s
i
gna
l
i
nto U 4 (U 5) for A G C mode operat
i
on or
bypasses the operat
i
ona
l
amp
li
f
i
er cha
i
n. The s
i
gna
l
then goes
i
nto the A /D
converter U 1 (U 2) w here
i
t
i
s d
i
g
i
t
i
zed us
i
ng a dua
l
s
l
ope
i
ntegrat
i
ng converter.
TP1 (TP2) are test po
i
nts w h
i
ch w hen used
i
n con
j
unct
i
on w
i
th TP3, (ana
l
og
ground), enab
l
e the user to mon
i
tor the actua
l
vo
l
tage be
i
ng presented to the card.
TP4 (TP5) are test po
i
nts w h
i
ch w hen used
i
n con
j
unct
i
on w
i
th TP3, (ana
l
og
ground), enab
l
e the user to mon
i
tor the vo
l
tage be
i
ng presented to the A /D
converter. Th
i
s can vary from the
i
nput at TP1 (TP2)
i
f the A G C mode
i
s se
l
ected.
Summary of Contents for VertexRSI 7200
Page 15: ...INTRODUCTION 1 4 THIS PA GE INTENTIONALLY LEFT BLANK...
Page 21: ...O VERVIEW 2 6 Figure 2 3 7200 A CU Functional Block Diagram...
Page 41: ...O VERVIEW 2 26 THIS PAGE INTENTIONALLY LEFT BLANK...
Page 46: ...THEORY 3 5...
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Page 154: ...7200 M AINTENANCE 7 2 THIS PA GE INTENTIONALLY LEFT BLANK...
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