Page 9
TMP89FM42
RA001
2. CPU Core
2.1
Configuration
The CPU core consists of a CPU, a system clock controller and a reset circuit.
This chapter describes the CPU core address space, the system clock controller and the reset circuit.
2.2
Memory space
The 870/C1 CPU memory space consists of a code area to be accessed as instruction operation codes and operands
and a data area to be accessed as sources and destinations of transfer and calculation instructions.
Both the code and data areas have independent 64-Kbyte address spaces.
2.2.1
Code area
The code area stores operation codes, operands, vector tables for vector call instructions and interrupt vector
tables.
The RAM, the BOOTROM and the Flash are mapped in the code area.
Note: Only the first 2 Kbytes of the BOOTROM are mapped in the memory map, except in the serial PROM mode.
Figure 2-1 Memory Map in the Code Area
0x0000
SWI instruction
(0xFF) is fetched.
SWI instruction
(0xFF) is fetched.
SWI instruction
(0xFF) is fetched.
0x003F
0x0040
RAM
(2048 bytes)
RAM
(2048 bytes)
0x083F
SWI instruction
(0xFF) is fetched.
SWI instruction
(0xFF) is fetched.
SWI instruction
(0xFF) is fetched.
0x1000
BOOTROM
(2048 bytes)
BOOTROM
(2048 bytes)
0x17FF
0x1800
0x7FFF
0x8000
Flash
(32768 bytes)
Flash
(32768 bytes)
Flash
(32768 bytes)
Flash
(32768 bytes)
0xFFA0
Vector table for vec-
tor call instructions
(32 bytes)
Vector table for vec-
tor call instructions
(32 bytes)
Vector table for vec-
tor call instructions
(32 bytes)
Vector table for vec-
tor call instructions
(32 bytes)
0xFFBF
0xFFCC
Interrupt vector
table
(52 bytes)
Interrupt vector
table
(52 bytes)
Interrupt vector
table
(52 bytes)
Interrupt vector
table
(52 bytes)
0xFFFF
Immediately after re-
set release
When the RAM is
mapped in the code
area
When the
BOOTROM is
mapped in the code
area
When the RAM and
the BOOTROM are
mapped in the code
area
Summary of Contents for TLCS-870/C1 Series
Page 1: ...8 Bit Microcontroller TLCS 870 C1 Series TMP89FM42 查询TMP89FM42供应商 捷多邦 专业PCB打样工厂 24小时加急出货 ...
Page 3: ...Revision History Date Revision 2007 10 25 1 First Release 2007 11 3 2 Contents Revised ...
Page 4: ......
Page 14: ......
Page 18: ...1 3 Block Diagram TMP89FM42 1 3 Block Diagram Figure 1 2 Block Diagram ...
Page 22: ...1 4 Pin Names and Functions TMP89FM42 ...
Page 60: ...2 CPU Core 2 5 Revision History TMP89FM42 ...
Page 76: ...3 Interrupt Control Circuit 3 8 Revision History TMP89FM42 ...
Page 86: ...4 External Interrupt control circuit 4 3 Function TMP89FM42 ...
Page 102: ...7 Voltage Detection Circuit 7 5 Revision History TMP89FM42 ...
Page 126: ...8 I O Ports 8 3 I O Port Registers TMP89FM42 Note 2 i 0 to 1 ...
Page 136: ...8 I O Ports 8 5 Revision History TMP89FM42 ...
Page 142: ...9 Special Function Registers 9 3 SFR3 0x0E40 to 0x0EFF TMP89FM42 ...
Page 146: ...10 Low Power Consumption Function for Peripherals TMP89FM42 ...
Page 149: ...TMP89FM42 11 3 Revision History Rev Description RA001 Deleted SLEEP2 description ...
Page 150: ...11 Divider Output DVO 11 3 Revision History TMP89FM42 ...
Page 220: ...15 Real Time Clock RTC 15 4 Real Time Clock Operation TMP89FM42 ...
Page 250: ...16 Asynchronous Serial Interface UART 16 15 Revision History TMP89FM42 ...
Page 302: ...18 Serial Bus Interface SBI 18 7 Revision History TMP89FM42 ...
Page 338: ...21 Flash Memory 21 4 Toggle Bit D6 TMP89FM42 ...
Page 384: ...22 Serial PROM Mode 22 15 Revision History TMP89FM42 ...
Page 388: ...24 Input Output Circuit 24 1 Control Pins TMP89FM42 ...
Page 404: ...25 Electrical Characteristics 25 11 Revision History TMP89FM42 ...
Page 406: ...26 Package Dimensions TMP89FM42 ...
Page 408: ......