Toshiba TLCS-870/C1 Series, Manual

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Page 22
2. CPU Core
2.3 System clock controller
TMP89FM42
RA001
Note 2: The clock output from the oscillation circuit is used as the input clock to the warm-up counter. The warm-up time contains
errors because the oscillation frequency is unstable until the oscillation circuit becomes stable. Set the sufficient time for
the oscillation start property of the oscillator.
2.3.4.2 Warm-up counter operation when the oscillation is enabled by the software
The warm-up counter serves to secure the time after the oscillation is enabled by the software before the
oscillation becomes stable, at a mode change from NORMAL1 to NORMAL2 or from SLOW1 to
SLOW2.
Select the input clock to the frequency division circuit at WUCCR<WUCSEL>.
Select the input clock to the 14-stage counter at WUCCR<WUCDIV>.
After the warm-up time is set at WUCDR, setting SYSCR2<XEN> or SYSCR2<XTEN> to "1" allows
the stopped oscillation circuit to start oscillation and the 14-stage counter to start counting the selected
input clock.
When the upper 8 bits of the counter become equal to WUCDR, an INTWUC interrupt occurs, counting
is stopped and the counter is cleared.
Set WUCCR<WUCRST> to "1" to discontinue the warm-up operation.
By setting it to "1", the count-up operation is stopped, the warm-up counter is cleared, and
WUCCR<WUCRST> is cleared to "0".
SYSCR2<XEN> and SYSCR2<XTEN> hold the values when WUCCR<WUCRST> is set to "1". To
restart the warm-up operation, SYSCR2<XEN> or SYSCR2<XTEN> must be cleared to "0".
Note: The warm-up counter starts counting when SYSCR2<XEN> or SYSCR2<XTEN> is changed from "0"
to "1". The counter will not start counting by writing "1" to SYSCR2<XEN> or SYSCR2<XTEN> when it
is in the state of "1".
Note: The clock output from the oscillation circuit is used as the input clock to the warm-up counter. The
warm-up time contains errors because the oscillation frequency is unstable until the oscillation circuit
becomes stable. Set the sufficient time for the oscillation start property of the oscillator.
2.3.5 Operation mode control circuit
The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and low-
frequency clocks, and switches the main system clock (fm).
There are three operating modes: the single-clock mode, the dual-clock mode and the STOP mode. These
modes are controlled by the system control registers (SYSCR1 and SYSCR2).
Figure 2-7 shows the operating mode transition diagram.
2.3.5.1 Single-clock mode
Only the gear clock (fcgck) is used for the operation in the single-clock mode.
WUCCR<WUCSEL> WUCCR<WUCDIV> Counter input clock Warm-up time
0
00 fc
2
6
/ fc to 255 x 2
6
/ fc
01 fc / 2
2
7
/ fc to 255 x 2
7
/ fc
10
fc / 2
2
2
8
/ fc to 255 x 2
8
/ fc
11
fc / 2
3
2
9
/ fc to 255 x 2
9
/ fc
1
00 fs
2
6
/ fs to 255 x 2
6
/ fs
01 fs / 2
2
7
/ fs to 255 x 2
7
/ fs
10
fs / 2
2
2
8
/ fs to 255 x 2
8
/ fs
11
fs / 2
3
2
9
/ fs to 255 x 2
9
/ fs