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TMP89FM42

RA001

13.4.1.4 Register buffer configuration

(1)

Temporary buffer

The TMP89FM42 contains an 8-bit temporary buffer. When a write instruction is executed on

TA0DRAL, the data is first stored into this temporary buffer, whether the double buffer is enabled or
disabled. Subsequently, when a write instruction is executed on TA0DRAH, the set value is stored
into the double buffer or TA0DRAH. At the same time, the set value in the temporary buffer is stored
into the double buffer or TA0DRAL. (This structure is designed to enable the set values of the lower-
level and higher-level registers simultaneously.) Therefore, when setting data to TA0DRA, be sure to
write the data into TA0DRAL and TA0DRAH in this order.

See Figure 13-1 for the temporary buffer configuration.

(2)

Double buffer

In the TMP89FM42, the double buffer can be used by setting TA0CR<TA0DBF>. Setting

TA0CR<TA0DBF> to "0" disables the double buffer. Setting TA0CR<TA0DBF> to "1" enables the
double buffer.

See Figure 13-1 for the double buffer configuration.

- When the double buffer is enabled

When a write instruction is executed on TA0DRAH during the timer operation, the set

value is first stored into the double buffer, and TA0DRAH/L are not updated immediately.
TA0DRAH/L compare the up counter value to the last set values. If the values are matched,
an INTTCA0 interrupt request is generated and the double buffer set value is stored in
TA0DRAH/L. Subsequently, the match detection is executed using a new set value.

When a read instruction is executed on TA0DRAH/L, the double buffer value (the last set

value) is read, rather than the TA0DRAH/L values (the current effective values).

When a write instruction is executed on TA0DRAH/L while the timer is stopped, the set

value is immediately stored into both the double buffer and TA0DRAH/L.

- When the double buffer is disabled

When a write instruction is executed on TA0DRAH during the timer operation, the set

value is immediately stored into TA0DRAH/L. Subsequently, the match detection is exe-
cuted using a new set value.

If the values set to TA0DRAH/L are smaller than the up counter value, the match detection

is executed using a new set value after the up counter overflows. Therefore, the interrupt
request interval may be longer than the selected time. If that is a problem, enable the double
buffer.

When a write instruction is executed on TA0DRAH/L while the timer is stopped, the set

value is immediately stored into TA0DRAH/L.

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Summary of Contents for TLCS-870/C1 Series

Page 1: ...8 Bit Microcontroller TLCS 870 C1 Series TMP89FM42 查询TMP89FM42供应商捷多邦专业PCB打样工厂 24小时加急出货 ...

Page 2: ...or usage in equipment that requires extraordinarily high quality and or reliability or a malfunction or failure of which may cause loss of human life or bodily injury Unintended Usage Unintended Usage include atomic energy control instruments airplane or spaceship instruments transportation instruments traffic signal instruments combustion control instruments medical instruments all types of safet...

Page 3: ...Revision History Date Revision 2007 10 25 1 First Release 2007 11 3 2 Contents Revised ...

Page 4: ......

Page 5: ...n the oscillation is enabled by the software 2 3 5 Operation mode control circuit 22 2 3 5 1 Single clock mode 2 3 5 2 Dual clock mode 2 3 5 3 STOP mode 2 3 5 4 Transition of operation modes 2 3 6 Operation Mode Control 27 2 3 6 1 STOP mode 2 3 6 2 IDLE1 2 and SLEEP1 modes 2 3 6 3 IDLE0 and SLEEP0 modes 2 3 6 4 SLOW mode 2 4 Reset Control Circuit 38 2 4 1 Configuration 38 2 4 2 Control 38 2 4 3 Fu...

Page 6: ...n 67 4 3 2 External interrupt 0 68 4 3 3 External interrupts 1 2 3 68 4 3 3 1 Interrupt request signal generating condition detection function 4 3 3 2 A noise canceller pass signal monitoring function when interrupt request signals are generated 4 3 3 3 Noise cancel time selection function 4 3 4 External interrupt 4 69 4 3 4 1 Interrupt request signal generating condition detection function 4 3 4 ...

Page 7: ...to generate voltage detection reset signals 85 7 5 Revision History 87 8 I O Ports 8 1 I O Port Control Registers 90 8 2 List of I O Port Settings 91 8 3 I O Port Registers 94 8 3 1 Port P0 P03 to P00 94 8 3 2 Port P1 P13 to P10 98 8 3 3 Port P2 P27 to P20 101 8 3 4 Port P4 P47 to P40 105 8 3 5 Port P7 P77 to P70 108 8 3 6 Port P8 P81 to P80 110 8 3 7 Port P9 P91 to P90 113 8 3 8 Port PB PB7 to PB...

Page 8: ...r buffer configuration 13 4 4 Window mode 156 13 4 4 1 Setting 13 4 4 2 Operation 13 4 4 3 Auto capture 13 4 4 4 Register buffer configuration 13 4 5 Pulse width measurement mode 158 13 4 5 1 Setting 13 4 5 2 Operation 13 4 6 Programmable pulse generate PPG mode 160 13 4 6 1 Setting 13 4 6 2 Operation 13 4 6 3 Register buffer configuration 13 5 Noise Canceller 163 13 5 1 Setting 163 13 6 Revision ...

Page 9: ...bling disabling the real time clock operation 204 15 3 3 Selecting the interrupt generation interval 204 15 4 Real Time Clock Operation 205 15 4 1 Enabling the real time clock operation 205 15 4 2 Disabling the real time clock operation 205 16 Asynchronous Serial Interface UART 16 1 Configuration 208 16 2 Control 209 16 3 Low Power Consumption Function 213 16 4 Protection to Prevent UART0CR1 and U...

Page 10: ...mpletion of reception 17 5 2 4 Stopping the receive operation 17 5 3 8 bit transmit receive mode 254 17 5 3 1 Setting 17 5 3 2 Starting the transmit receive operation 17 5 3 3 Transmit buffer and shift operation 17 5 3 4 Operation on completion of transmission reception 17 5 3 5 Stopping the transmit receive operation 17 6 AC Characteristics 259 17 7 Revision History 260 18 Serial Bus Interface SB...

Page 11: ...bit AD Converter ADC 20 1 Configuration 293 20 2 Control 294 20 3 Functions 298 20 3 1 Single mode 298 20 3 2 Repeat mode 298 20 3 3 AD operation disable and forced stop of AD operation 299 20 4 Register Setting 300 20 5 Starting STOP IDLE0 SLOW Modes 300 20 6 Analog Input Voltage and AD Conversion Result 301 20 7 Precautions about the AD Converter 302 20 7 1 Analog input pin voltage range 302 20 ...

Page 12: ...2 8 3 Flash memory read command operation command 0x40 340 22 8 4 RAM loader command operation command 0x60 342 22 8 5 Flash memory SUM output command operation command 0x90 344 22 8 6 Product ID code output command operation command 0xC0 345 22 8 7 Flash memory status output command 0xC3 347 22 8 7 1 Flash memory status code 22 8 8 Mask ROM emulation setting command 0xD0 350 22 8 9 Flash memory s...

Page 13: ...m Ratings 375 25 2 Operating Conditions 376 25 2 1 MCU mode Flash Programming or erasing 376 25 2 2 MCU mode Except Flash Programming or erasing 377 25 2 3 Serial PROM mode 378 25 3 DC Characteristics 379 25 4 AD Conversion Characteristics 382 25 5 Power on Reset Circuit Characteristics 383 25 6 Voltage Detecting Circuit Characteristics 384 25 7 AC Characteristics 385 25 7 1 MCU mode Flash program...

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Page 15: ...ted in this document shall be made at the customer s own risk 021023_B The products described in this document shall not be used or embedded to any downstream products of which manufacture use and or sale are prohibited under any applicable laws and regulations 060106_Q The information contained herein is presented only as a guide for the applications of our products No responsibility is assumed b...

Page 16: ...cy clock High frequency clock stop SLOW2 mode Low power consumption operation using low frequency clock High frequency clock oscillate IDLE0 mode CPU stops and only the Time Based Timer TBT on peripherals operate using high frequency clock Released when the reference time set to TBT has elapsed IDLE1 mode The CPU stops and peripherals operate using high frequency clock Release by interruputs CPU r...

Page 17: ... P76 INT3 P45 AIN5 KWI5 P43 AIN3 KWI3 P42 AIN2 KWI2 TXD1 RXD1 P91 PWM02 PPG02 TC02 P80 PWM03 PPG03 TC03 P81 PWM00 PPG00 TC00 P70 PPGA0 TCA0 P72 PPGA1 TCA1 P73 SO0 RXD0 TXD0 PB4 SI0 TXD0 RXD0 PB5 SCLK0 PB6 PB7 PWM01 PPG01 TC01 P71 VSS XOUT P01 MODE VDD XTIN P02 XTOUT P03 RESET P10 STOP INT5 P11 INT0 P12 INT1 P13 XIN P00 P20 TXD0 RXD0 SO0 OCDCK P22 SCLK0 P23 SDA0 SO0 P24 SCL0 SI0 P26 P27 VAREF AVDD ...

Page 18: ...1 3 Block Diagram TMP89FM42 1 3 Block Diagram Figure 1 2 Block Diagram ...

Page 19: ...INT5 STOP IO I I PORT11 External interrupt 5 input STOP mode release input P10 RESET IO I PORT10 Reset signal input P27 IO PORT27 P26 IO PORT26 P25 SCLK0 IO IO PORT25 Serial clock input output 0 P24 SCL0 SI0 IO IO I PORT24 I2C bus clock input output 0 Serial data input 0 P23 SDA0 SO0 IO IO O PORT23 I2C bus data input output 0 Serial data output 0 P22 SCLK0 IO IO PORT22 Serial clock input output 0 ...

Page 20: ...4 input P76 INT3 IO I PORT76 External interrupt 3 input P75 INT2 IO I PORT75 External interrupt 2 input P74 DVO IO O PORT74 Divider output P73 TCA1 PPGA1 IO I O PORT73 TCA1 input PPGA1 output P72 TCA0 PPGA0 IO I O PORT72 TCA0 input PPGA0 output P71 TC01 PPG01 PWM01 IO I O O PORT71 TC01 input PPG01 output PWM01 output P70 TC00 PPG00 PWM00 IO I O O PORT70 TC00 input PPG00 output PWM00 output P81 TC0...

Page 21: ...ta input 0 UART data output 0 Serial data input 0 PB4 TXD0 RXD0 SO0 IO O I O PORTB4 UART data output 0 UART data input 0 Serial data output 0 MODE I Test pin for out going test fix to Low level VAREF AVDD I Analog reference voltage input pin for A D conversion Ana log power supply pin VDD I VDD pin VSS I GND pin Table 1 1 Pin Names and Functions 3 3 Pin Name Input Output Functions ...

Page 22: ...1 4 Pin Names and Functions TMP89FM42 ...

Page 23: ... the serial PROM mode Figure 2 1 Memory Map in the Code Area 0x0000 SWI instruction 0xFF is fetched SWI instruction 0xFF is fetched SWI instruction 0xFF is fetched 0x003F 0x0040 RAM 2048 bytes RAM 2048 bytes 0x083F SWI instruction 0xFF is fetched SWI instruction 0xFF is fetched SWI instruction 0xFF is fetched 0x1000 BOOTROM 2048 bytes BOOTROM 2048 bytes 0x17FF 0x1800 0x7FFF 0x8000 Flash 32768 byte...

Page 24: ...CGCKSEL 00 Otherwise IRSTSR FCLR may be enabled at unexpected timing In the serial PROM mode the RAM is mapped to 0x0040 to 0x083F in the code area regardless of the value of SYSCR3 RAREA The program can be executed on the RAM using the RAM loader function Note 1 When the RAM is not mapped in the code area the SWI instruction is fetched from 0x0040 to 0x083F Note2 The contents of the RAM become un...

Page 25: ...SYSCR3 RAREA data is 1 RVCTRS Status of mapping of the vector address in the area 0 1 The enabled SYSCR3 RVCTR data is 0 The enabled SYSCR3 RVCTR data is 1 Example Program transfer Transfer the program saved in the data area to the RAM LD HL TRANSFER_START_ADDRESS Destination RAM address LD DE PROGRAM_START_ADDRESS Source ROM address LD BC BYTE_OF_PROGRAM Number of bytes of the program to be execu...

Page 26: ...e 2 2 Memory Map in the Data Area Flash memory control register 2 FLSCR2 7 6 5 4 3 2 1 0 0x0FD1 Bit Symbol CR1EN Read Write W After reset CR1EN FLSCR1 register enable disable control 0xD5 Others Enable a change in the FLSCR1 setting Reserved 0x0000 SFR1 64 bytes SFR1 64 bytes 0x003F 0x0040 RAM 2048 bytes RAM 2048 bytes 0x083F 0xFF is read 0xFF is read 0x0E40 SFR3 192 bytes SFR3 192 bytes 0x0EFF 0x...

Page 27: ...P_ADDRESS Head of address of the RAM to be initialized LD A 0x00 Initialization data LD BC BYTE_OF_CLEAR_BYTES Number of bytes of RAM to be initialized 1 CLR_RAM LD HL A Initialization of the RAM INC HL Initialization address increment DEC BC Have all the RAMs been initialized JRS F CLR_RAM Setting FLSMD BAREA to 1 maps the BOOTROM to 0x1000 to 0x17FF in the code area and to 0x1000 to 0x17FF in th...

Page 28: ...Memory space TMP89FM42 2 2 2 4 Flash The Flash is mapped to 0x8000 to 0xFFFF in the data area after reset release CR1EN FLSCR1 register enable disable control 0xD5 Others Enable a change in the FLSCR1 setting Reserved ...

Page 29: ...0 0 0 1 0 0 0 STOP Activates the STOP mode 0 1 Operate the CPU and the peripheral circuits Stop the CPU and the peripheral circuits activate the STOP mode RELM Selects the STOP mode release method 0 1 Edge sensitive release mode Release the STOP mode at the rising edge of the STOP mode release signal Level sensitive release mode Release the STOP mode at the H level of the STOP mode release signal ...

Page 30: ...uency clock Hz fs Low frequency clock Hz Note 2 WUCCR WUCRST is cleared to 0 automatically and need not be cleared to 0 after being set to 1 Note 3 Bits 7 to 4 of WUCCR are read as 0 Bit 0 is read as 1 Note 4 Before starting the warm up counter operation set the source clock and the frequency division rate at WUCCR and set the warm up time at WUCDR System control register 2 SYSCR2 0x0FDD 7 6 5 4 3...

Page 31: ...et P0FC2 to 1 and then set SYSCR2 XTEN to 1 The high frequency fc clock and the low frequency fs clock can easily be obtained by connecting an oscillator between the XIN and XOUT pins and between the XTIN and XTOUT pins respectively Clock input from an external oscillator is also possible In this case external clocks are applied to the XIN XTIN pins and the XOUT XTOUT pins are kept open Enabling d...

Page 32: ...ion becomes as shown in Table 2 1 and a system clock reset occurs For details of clock switching refer to 2 3 6 Operation Mode Control Figure 2 4 Examples of Oscillator Connection 2 3 3 2 Clock gear The clock gear is a circuit that selects a gear clock fcgck obtained by dividing the high frequency clock fc and inputs it to the timing generator Selects a divided clock at CGCR FCGCKSEL Two machine c...

Page 33: ...counter 1 Main system clock generator This circuit selects the gear clock fcgck or the clock that is a quarter of the low frequency clock fs for the main system clock fm to operate the CPU core Clearing SYSCR2 SYSCK to 0 selects the gear clock fcgck Setting it to 1 selects the clock that is a quarter of the low frequency clock fs It takes a certain period of time after SYSCR2 SYSCK is changed befo...

Page 34: ...0 C1 Series 10 types ranging from 1 cycle instructions which require one machine cycle for execution to 10 cycle instructions which require 10 machine cycles for execution and 13 cycle instructions which require 13 machine cycles for execution 2 3 4 Warm up counter The warm up counter is a circuit that counts the high frequency clock fc and the low frequency clock fs and it consists of a source cl...

Page 35: ...he warm up counter serves to secure the time after the oscillation is enabled by the hardware before the oscillation becomes stable at the release of the STOP mode The high frequency clock fc or the low frequency clock fs which generates the main system clock when the STOP mode is activated is selected as the input clock for frequency division circuit regardless of WUCCR WUCSEL Before the STOP mod...

Page 36: ... 0 SYSCR2 XEN and SYSCR2 XTEN hold the values when WUCCR WUCRST is set to 1 To restart the warm up operation SYSCR2 XEN or SYSCR2 XTEN must be cleared to 0 Note The warm up counter starts counting when SYSCR2 XEN or SYSCR2 XTEN is changed from 0 to 1 The counter will not start counting by writing 1 to SYSCR2 XEN or SYSCR2 XTEN when it is in the state of 1 Note The clock output from the oscillation...

Page 37: ...peripheral circuits stop except the oscillation circuits and the time base timer In the IDLE0 mode the peripheral circuits stop in the states when the IDLE0 mode is activated or become the same as the states when a reset is released For operations of the peripheral circuits in the IDLE0 mode refer to the section of each peripheral circuit The IDLE0 mode is activated by setting SYSCR2 TGHALT to 1 i...

Page 38: ...e SLOW mode some peripheral circuits become the same as the states when a reset is released For operations of the peripheral circuits in the SLOW mode refer to the section of each peripheral circuit Set SYSCR2 SYSCK to switch the operation mode from NORMAL2 to SLOW2 or from SLOW2 to NORMAL2 In the SLOW2 mode outputs of the prescaler and stages 1 to 8 of the divider stop 3 SLOW1 mode In this mode t...

Page 39: ...ame as the states when a reset is released For operations of the peripheral circuits in the SLEEP0 mode refer to the section of each peripheral circuit The SLEEP0 mode can be activated and released in the same way as for the IDLE0 mode The operation returns to the SLOW1 mode after this mode is released In the SLEEP0 mode the CPU stops and the timing generator stops the clock supply to the periph e...

Page 40: ...at TBTCR TBTCK Figure 2 7 Operation Mode Transition Diagram IDLE0 mode RESET Warm up that follows reset release NORMAL1 mode STOP NORMAL2 mode SLOW2 mode SLOW1 mode IDLE0 mode IDLE2 mode SLEEP1 mode SLEEP0 mode a Single clock mode b Dual clock mode SYSCR2 IDLE 1 SYSCR1 STOP 1 SYSCR2 IDLE 1 SYSCR1 STOP 1 SYSCR2 IDLE 1 SYSCR1 STOP 1 Interrupt Interrupt STOP mode release signal STOP mode release sign...

Page 41: ... STOP mode The STOP mode is released by the following STOP mode release signals It is also released by a reset by the RESET pin a power on reset and a reset by the voltage detection circuits When a reset is released the warm up starts After the warm up is completed the NORMAL1 mode becomes active 1 Release by the STOP pin Table 2 3 Operation Modes and Conditions Operation mode Oscillation circuit ...

Page 42: ...the STOP pin high Setting SYSCR1 RELM to 1 selects the level sensitive release mode This mode is used for the capacitor backup when the main power supply is cut off and the long term battery backup Even if an instruction for starting the STOP mode is executed while the STOP pin in put is high the STOP mode does not start Thus to start the STOP mode in the level sensitive release mode it is necessa...

Page 43: ... rising edge of the STOP pin input Setting SYSCR1 RELM to 0 selects the edge sensitive release mode This is used in applications where a relatively short program is executed repeatedly at periodic intervals This periodic signal for example a clock from a low power con sumption oscillator is input to the STOP pin In the edge sensitive release mode the STOP mode is started even when the STOP pin inp...

Page 44: ...ation The STOP mode is released in the following sequence 1 Oscillation starts For the oscillation start operation in each mode refer to Table 2 4 Oscil lation Start Operation at Release of the STOP Mode 2 Warm up is executed to secure the time required to stabilize oscillation The internal opera tions remain stopped during warm up The warm up time is set by the warm up counter depending on the os...

Page 45: ...ad of the instruction which starts the IDLE1 2 or SLEEP1 mode Table 2 4 Oscillation Start Operation at Release of the STOP Mode Operation mode before the STOP mode is started High frequency clock Low frequency clock Oscillation start operation after release Single clock mode NORMAL1 High frequency clock oscillation circuit The high frequency clock oscillation circuit starts oscillation The low fre...

Page 46: ... and WDT stop Interrupt processing Reset Yes No No No No IMF 1 Reset input Yes Yes Interrupt release mode Normal release mode Interrupt request Starting IDLE1 2 mode or SLEEP1 mode by an instruction Execution of the instruction which follows the IDLE1 2 mode or SLEEP1 mode start instruction ...

Page 47: ...T pin a power on reset and a reset by the voltage detection circuits After releasing the reset the warm up starts After the warm up is completed the NORMAL1 mode becomes active Normal release mode IMF 0 The IDLE1 2 or SLEEP1 mode is released when the interrupt latch enabled by the individ ual interrupt enable flag EF is 1 The operation is restarted by the instruction that follows the IDLE1 2 or SL...

Page 48: ...red to 0 and the opera tion mode is returned to the mode preceding the IDLE0 or SLEEP0 mode If TBTCR TBTEN has been set at 1 the INTTBT interrupt latch is set The IDLE0 and SLEEP0 modes are also released by a reset by the RESET pin a power on reset and a reset by the voltage detection circuits When a reset is released the warm up starts After the warm up is completed the NORMAL1 mode becomes activ...

Page 49: ...ock fm is switched to fs 4 After switching wait for 2 machine cycles or longer and then clear SYSCR2 XEN to 0 to turn off the high frequency clock oscillator If the oscillation of the low frequency clock fs is unstable confirm the stable oscillation at the warm up counter before implementing the procedure described above Note 1 Be sure to follow this procedure to switch the operation from the NORM...

Page 50: ...5 fcgck s or shorter Note 4 When P0FC0 is 0 setting SYSCR2 XEN to 1 causes a system clock reset Note 5 When SYSCR2 XEN is set at 1 writing 1 to SYSCR2 XEN does not cause the warm up counter to start counting the source clock Example 1 Switching from the NORMAL2 mode to the SLOW1 mode when fc is used as the basic clock for the high fre quency clock SET SYSCR2 4 SYSCR2 SYSCK 1 Switches the main syst...

Page 51: ... round up to 0x9D SET EIRL 4 Enables INTWUC interrupts SET SYSCR2 6 SYSCR2 XEN 1 Starts the oscillation of the high frequency clock oscillation circuit Interrupt service routine of warm up counter interrupts PINTWUC CLR SYSCR2 4 SYSCR2 SYSCK 0 Switches the main system clock to the gear clock NOP Waits for 2 machine cycles NOP CLR SYSCR2 5 SYSCR2 XTEN 0 Turns off the low frequency clock oscillation...

Page 52: ...te 1 The enabled SYSCR3 RSTDIS is initialized by a power on reset only and cannot be initialized by an external reset input or internal factor reset The value written in SYSCR3 is reset by a power on reset external reset input or internal factor reset Note 2 The value of SYSCR3 RSTDIS is invalid until 0xB2 is written into SYSCR4 System control register 3 SYSCR3 0x0FDE 7 6 5 4 3 2 1 0 Bit Symbol RV...

Page 53: ...e enabled SYSCR3 RSTDIS is initialized by a power on reset only and cannot be initialized by any other reset sig nals The value written in SYSCR3 is reset by a power on reset and other reset signals Note 2 Bits 7 to 3 of SYSCR4 are read as 0 System control register 4 SYSCR4 0x0FDF 7 6 5 4 3 2 1 0 Bit Symbol SYSCR4 Read Write W After reset 0 0 0 0 0 0 0 0 SYSCR4 Writes the SYSCR3 data control code ...

Page 54: ...eration that follows reset release the trimming data is loaded from the non volatile exclusive use memory for adjustment of the ladder resistor that generates the comparison voltage for the power on reset and the voltage detection circuits When the warm up operation that follows reset release is finished the CPU starts execution of the program from the reset vector address stored in addresses 0xFF...

Page 55: ...ration that fol lows reset release Program counter PC MCU mode 0xFFFE Serial PROM mode 0x01FF MCU mode 0xFFFE Serial PROM mode 0x01FF MCU mode 0xFFFE Serial PROM mode 0x01FF Stack pointer SP 0x00FF 0x00FF 0x00FF RAM Indeterminate Indeterminate Indeterminate General purpose registers W A B C D E H L IX and IY Indeterminate Indeterminate Indeterminate Register bank selector RBS 0 0 0 Jump status fla...

Page 56: ...n is turned to H Figure 2 15 External Reset Input when the power is turned on Figure 2 16 External Reset Input when the power is stabilized Reset time Warm up operation During reset CPU and peripheral circuits start operation Operating voltage RESET pin CPU peripheral circuits reset Reset time Warm up operation During reset CPU and peripheral circuits start operation RESET pin Reset signal Operati...

Page 57: ... 6 Trimming data reset The trimming data reset is an internal factor reset that occurs when the trimming data latched in the internal circuit is broken down during operation due to noise or other factors The trimming data is a data bit provided for adjustment of the ladder resistor that generates the compar ison voltage for the power on reset and the voltage detection circuits This bit is loaded f...

Page 58: ... warm up operation that follows reset release is finished After the warm up operation that follows reset release is finished set P1PU0 to 1 and P1CR0 to 0 and connect a pull up resistor for a port Then set SYSCR3 RSTDIS to 1 and write 0xB2 to SYSCR4 This disables the external reset function and makes the external reset input pin usable as a normal port To use the pin as an external reset pin when ...

Page 59: ...1 Warm up counter operation when the oscillation is enabled by the hardware Fixed specification from T B D to 0x66 Figure 2 15 External Reset Input when the power is turned on and Figure 2 16 External Reset Input when the power is stabilized Deleted Recommended ...

Page 60: ...2 CPU Core 2 5 Revision History TMP89FM42 ...

Page 61: ...ources Enable condition Interrupt latch Vector Address MCU mode Basic prior ity RVCTR 0 enabled RVCTR 1 enabled Internal External Reset Non maskable 0xFFFE 1 Internal INTSWI Non maskable 0xFFFC 0x01FC 2 Internal INTUNDEF Non maskable 0xFFFC 0x01FC 2 Internal INTWDT Non maskable ILL IL3 0xFFF8 0x01F8 2 Internal INTWUC IMF AND EIRL EF4 1 ILL IL4 0xFFF6 0x01F6 5 Internal INTTBT IMF AND EIRL EF5 1 ILL...

Page 62: ...ontrol Circuit TMP89FM42 Note 4 Do not set SYSCR3 RVCTR to 0 in the serial PROM mode If an interrupt is generated with SYSCR3 RVCTR 0 the software refers to the vector area in the BOOTROM and the user cannot use it ...

Page 63: ...ecoder Vector address generation Priority encoder DI instruction Interrupt accept IDLE1 2 SLEEP1 2 Mode clear request Interrupt request IMF Interrupt master enable flag Internal factor reset Instruction to write 0 to IMF Non maskable interrupts Maskable interrupts Maskable interrupt priority change circuit ILPRS1 ILPRS2 ILPRS3 ILPRS4 S Q IL 3 R 5 4 3 1 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 D...

Page 64: ...t requests generated while the instruction is executed Interrupt latches cannot be set to 1 by using an instruction Writing 1 to an interrupt latch is equivalent to deny ing clearing of the interrupt latch and not setting the interrupt latch Since interrupt latches can be read by instructions the status of interrupt requests can be monitored by software Note In the main program before manipulating...

Page 65: ...ch was the status before interrupt acceptance reloaded on the IMF by return interrupt instruction RETI RETN The IMF is located on bit 0 in EIRL Address 0x03A in SFR and can be read and written by instructions The IMF is normally set and cleared by EI and DI instructions respectively During reset the IMF is initial ized to 0 3 3 2 Individual interrupt enable flags EF25 to EF4 Each of these flags en...

Page 66: ...LL ILL 7 6 5 4 3 2 1 0 0x0FE0 Bit Symbol IL7 IL6 IL5 IL4 IL3 Read Write R W R W R W R W R R R R After reset 0 0 0 0 0 0 0 0 Function INTTXD0 INTRXD0 INTSIO0 INTTBT INTWUC INTWDT Interrupt latch ILH ILH 7 6 5 4 3 2 1 0 0x0FE1 Bit Symbol IL15 IL14 IL13 IL12 IL11 IL10 IL9 IL8 Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Function INTSBI0 INTSIO0 INTTCA0 INTTC01 INTTC00 INTRTC...

Page 67: ...on INTTXD0 INTRXD0 INTSIO0 INTTBT INTWUC Interrupt master en able flag Interrupt enable register EIRH EIRH 7 6 5 4 3 2 1 0 0x003B Bit Symbol EF15 EF14 EF13 EF12 EF11 EF10 EF9 EF8 Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Function INTSBI0 INTSIO0 INTTCA0 INTTC01 INTTC00 INTRTC INTADC INTVLTD INT5 Interrupt enable register EIRE EIRE 7 6 5 4 3 2 1 0 0x003C Bit Symbol EF23...

Page 68: ...rrupt service routine the IMF becomes 0 automatically and need not be cleared to 0 normally How ever if using multiple interrupt in the interrupt service routine manipulate ILPRS1 to 6 before setting the IMF to 1 Interrupt priority change control register 1 ILPRS1 7 6 5 4 3 2 1 0 0x0FF0 Bit Symbol IL07P IL06P IL05P IL04P Read Write R W R W R W R W After reset 0 0 0 0 0 0 0 0 IL07P Sets the interru...

Page 69: ...5 7 6 5 4 3 2 1 0 0x0FF4 Bit Symbol IL23P IL22P IL21P IL20P Read Write R W R W R W R W After reset 0 0 0 0 0 0 0 0 IL23P Sets the interrupt priority of IL23 00 Level 0 lower priority IL22P Sets the interrupt priority of IL22 01 Level 1 IL21P Sets the interrupt priority of IL21 10 Level 2 IL20P Sets the interrupt priority of IL20 11 Level 3 higher priority Interrupt priority change control register...

Page 70: ... do so right after a reset or when the interrupt master enable flag IMF is 0 3 5 2 Interrupt acceptance processing Interrupt acceptance processing is packaged as follows 1 The interrupt master enable flag IMF is cleared to 0 in order to disable the acceptance of any fol lowing interrupt 2 The interrupt latch IL for the interrupt source accepted is cleared to 0 3 The contents of the program counter...

Page 71: ...nter PC and the program status word PSW includes IMF are automatically saved on the stack but the general purpose registers are not These registers must be saved by software if necessary When multiple interrupt services are nested it is also necessary to avoid using the same data memory area for saving registers The following methods are used to save restore the general purpose registers 3 5 3 1 U...

Page 72: ...end of the interrupt service task because executing the RETI instruction makes a return automatically to the register bank that was being used by the main task according to the content of the PSW Note Two register banks BANK0 and BANK1 are available Each bank consists of 8 bit general purpose registers W A B C D E H and L and 16 bit general purpose registers IX and IY Example Save store register u...

Page 73: ...ws RETI RETN Interrupt Return 1 Program counter PC and program status word register bank are restored from tha stack 2 Stack pointer SP is incremented by 3 Main task Interrupt service task Interrupt acceptance Interrupt return Switching occurs to the register bank BANK1 A return is made automatically to the register bank BANK0 LD RBS 1 The register bank BANK0 is in use ...

Page 74: ...ess error is detected The address error detection range can be further expanded by writing 0xFF to unused areas in the pro gram memory 3 6 2 Debugging Debugging efficiency can be increased by placing the SWI instruction at the software break point setting address 3 7 Undefined Instruction Interrupt INTUNDEF When the CPU tries to fetch and execute an instruction that is not defined INTUNDEF is gene...

Page 75: ...P89FM42 3 8 Revision History Rev Description RA003 Revised from WDTCR1 WDTOUT to WDCTR WDTOUT Added chapter 3 5 Interrupt Sequence Figure 3 3 Saving restoring general purpose registers Revised SP position ...

Page 76: ...3 Interrupt Control Circuit 3 8 Revision History TMP89FM42 ...

Page 77: ...se is removed by the noise canceller Figure 4 1 External Interrupts 0 5 Figure 4 2 External Interrupts 1 2 3 Figure 4 3 External Interrupt 4 Noise canceller INTj pin fs 4 fcgck INTj interr request j 0 5 Falling edge detection circuit Interrupt request signal generation circuit Noise canceller 3 4 2 1 fcgck fs 4 INTi pin INTiLVL INTiES INTi interrupt request i 1 to 3 A B C D S Z Rising edge detecti...

Page 78: ... interrupt When the operation mode is changed from NORMAL1 2 or IDLE1 2 to SLOW1 2 or SLEEP1 wait 12 fs s after the operation mode is changed and Low power consumption register 3 POFFCR3 7 6 5 4 3 2 1 0 0x0F77 Bit Symbol INT5EN INT4EN INT3EN INT2EN INT1EN INT0EN Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 INT5EN INT5 control 0 1 Disable Enable INT4EN INT4 control 0 1 Dis...

Page 79: ... requests may be generated when EINTCR2 is changed Before doing such operation clear the corresponding interrupt enable register to 0 to disable the generation of interrupt When the operation mode is changed from NORMAL1 2 or IDLE1 2 to SLOW1 2 or SLEEP1 wait 12 fs s after the operation mode is changed and clear the inter rupt latch And when the operation mode is changed from SLOW1 2 or SLEEP1 to ...

Page 80: ...clear the corresponding interrupt enable register to 0 to disable the generation of interrupt When the operation mode is changed from NORMAL1 2 or IDLE1 2 to SLOW1 2 or SLEEP1 wait 12 fs s after the operation mode is changed and clear the inter rupt latch And when the operation mode is changed from SLOW1 2 or SLEEP1 to NORMAL1 2 or IDLE1 2 wait 2 fcgck 3 fspl s after the operation mode is changed ...

Page 81: ...MAL1 2 or IDLE1 2 wait 2 fcgck 3 fspl s after the operation mode is changed and clear the interrupt latch Table 4 1 External Interrupts Source Pin Enable conditions Interrupt request signal generated at External interrupt pin input signal width and noise removal NORMAL1 2 IDLE1 2 SLOW1 2 SLEEP1 INT0 INT0 IMF AND EF16 1 Falling edge Less than 1 fcgck Noise More than 1 fcgck and less than 2 fcgck In...

Page 82: ...ion function Select interrupt request signal generating conditions at EINTCRx INTxES for external interrupts 1 2 3 Note x 1 to 3 4 3 3 2 A noise canceller pass signal monitoring function when interrupt request signals are generated The level of a signal that has passed through the noise canceller when an interrupt request is generated can be read by using EINTCRx INTxLVL When both edges are select...

Page 83: ... used as an output port the input signal to the port is fixed to L when the mode is switched to the output mode and thus an interrupt request occurs To use the pin as an out put port clear the corresponding interrupt enable register to 0 to disable the generation of interrupt Note 3 Interrupt requests may be generated during transition of the operation mode Before changing the operation mode clear...

Page 84: ...ime selection function In NORMAL1 2 or IDLE1 2 mode a signal that has been sampled by fcgck is sampled at the sampling interval selected at EINTCRx INT4NC If the same level is detected three consecutive times the signal is recognized as a signal If not the signal is removed as noise Table 4 4 Selection of Interrupt Request Generation Edge EINTCR4 INT4ES Detected at 00 Rising edge 01 Falling edge 1...

Page 85: ...he generation of interrupt Note 3 Interrupt requests may be generated during transition of the operation mode Before changing the operation mode clear the corresponding interrupt enable register to 0 to disable the generation of interrupt When the operation mode is changed from NORMAL1 2 or IDLE1 2 to SLOW1 2 or SLEEP1 wait 12 fs s after the operation mode is changed and clear the interrupt latch ...

Page 86: ...4 External Interrupt control circuit 4 3 Function TMP89FM42 ...

Page 87: ...hdog timer control code register WDCDR the watchdog timer counter monitor WDCNT and the watchdog timer status WDST The watchdog timer is enabled automatically just after the warm up operation that follows reset is finished Watchdog timer control register WDCTR 0x0FD4 7 6 5 4 3 2 1 0 Bit Symbol WDTEN WDTW WDTT WDTOUT Read Write R R R W R W R W R W After reset 1 0 1 0 0 1 1 0 Source clock Watchdog t...

Page 88: ...ng the clear code at a point within the first half of the overflow time of the 8 bit up counter The 8 bit up counter is cleared by writing the clear code after the first half of the overflow time has elapsed A watchdog timer interrupt request is generated by writing the clear code at a point within the first three quarters of the overflow time of the 8 bit up counter The 8 bit up counter is cleare...

Page 89: ... the 8 bit up counter occurs at the same time as 0xB1 disable code is written into WDCDR with WDCTR WDTEN set at 1 the watchdog timer operation is disabled preferentially and the overflow detection is not executed To re enable the watchdog timer operation set WDCTR WDTEN to 1 There is no need to write a con trol code into WDCDR Figure 5 2 WDCTR WDTEN Set Timing and Overflow Time Watchdog timer sta...

Page 90: ...WDCTR WDTW and the 8 bit up Counter Clear Time 5 3 3 Setting the overflow time of the 8 bit up counter WDCTR WDTT sets the overflow time of the 8 bit up counter When the 8 bit up counter overflows a watchdog timer reset request signal or a watchdog timer interrupt request signal occurs depending on the WDCTR WDTOUT setting If the watchdog timer interrupt request signal is selected as the malfuncti...

Page 91: ...quest signal resets the TMP89FM42 and starts the warm up operation 5 3 5 Writing the watchdog timer control codes The watchdog timer control codes are written into WDCDR By writing 0x4E clear code into WDCDR the 8 bit up counter is cleared to 0 and continues counting the source clock When WDCTR WDTEN is 0 writing 0xB1 disable code into WDCDR disables the watchdog timer operation To prevent the 8 b...

Page 92: ...eration for releasing the 8 bit up counter outside the clear time You can know which factor has caused a watchdog timer interrupt request signal by reading WDST WINTST2 and WDST WINTST1 in the watchdog timer interrupt service routine WDST WINTST2 and WDST WINTST1 are cleared to 0 when WDST is read If WDST is read at the same time as the condition for turning WDST WINTST2 or WDST WINTST1 to 1 is sa...

Page 93: ...eleasing voltage of the power on reset circuit a power on reset signal is released When power supply voltage goes down if the supply voltage is equal to or lower than the detecting voltage of the power on reset circuit a power on reset signal is generated Until the power on reset signal is generated a warm up circuit and a CPU is reset When the power on reset signal is released the warm up circuit...

Page 94: ...electrical characteristics and take them into consideration when designing equipment Note 2 For the AC timing refer to the electrical characteristics Figure 6 2 Operation Timing of Power on Reset Supply voltage VDD VPROFF Operating voltage VPRON VDD PPW PRON Warm up counter start PWUP PROFF Power on reset signal Warm up counter clock CPU peripheral circuits reset signal ...

Page 95: ...than the detec tion voltage VDxLVL a voltage detection interrupt request signal or a voltage detection reset signal is generated Either the voltage detection interrupt request signal or the voltage detection reset signal can be selected by pro gramming the software Figure 7 1 Voltage Detection Circuit 7 2 Control The voltage detection circuit is controlled by voltage detection control registers 1 ...

Page 96: ...D1SF Voltage detection 1 status flag Magnitude relation of VDD and VD1LVL when they are read 0 VDD VD1LVL 1 VDD VD1LVL VD1LVL Selection for detection voltage 1 00 4 50 0 2 0 2V 01 4 20 0 2 0 2V 10 3 70 0 2 0 2V 11 3 15 0 15 0 15V Voltage detection control register 2 VDCR2 0x0FC7 7 6 5 4 3 2 1 0 Bit Symbol SRSS VD2MOD VD2EN VD1MOD VD1EN Read Write R R R W R W R W R W R W After reset 0 0 0 0 0 0 0 0...

Page 97: ...t age detection reset signals are generated continuously as long as the supply voltage VDD is lower than the detection voltage VDxLVL Note If the voltage detection mode is set to generate voltage detection interrupt request signals and the supply volt age VDD becomes lower than the detection voltage VDxLVL in the STOP IDLE0 or SLEEP0 mode a volt age detection interrupt request signal is generated ...

Page 98: ...evel release mode is selected and the supply voltage VDD is equal to or higher than the detection voltage VDxLVL STOP mode cannot be activated Setting VDCR2 SRSS to 00 allows STOP mode to be released depending on the state of the STOP pin Setting it to 01 allows STOP mode to be released when the supply voltage VDD becomes equal to or higher than the detection voltage VDxLVL Setting it to 10 allows...

Page 99: ...luctuations in the system power supply and clear the interrupt latch 7 4 2 Setting procedure when the operation mode is set to generate voltage detection reset signals When the operation mode is set to generate voltage detection reset signals make the following setting 1 Clear the voltage detection circuit interrupt enable flag to 0 2 Set the detection voltage at VDCR1 VDxLVL x 1 to 2 3 Clear VDCR...

Page 100: ...Voltage Detection Circuit 7 4 Register Settings TMP89FM42 Note 2 The voltage detection reset signals are generated continuously as long as the supply voltage VDD is lower than the detection voltage VDxLVL ...

Page 101: ...TMP89FM42 7 5 Revision History Rev Description RA001 Voltage detection control register 1 Revised VD1LVL and VD2LVL RA002 Revised from VDCR2 VDxLVL to VDCR1 VDxLVL ...

Page 102: ...7 Voltage Detection Circuit 7 5 Revision History TMP89FM42 ...

Page 103: ...ort P0 P03 to P00 Note 4 Note Input output Also used as the high frequency oscillator connection pin and the low frequency oscillator connection pin Port P1 P13 to P10 4 Input output Also used as the external reset input the external interrupt input and the STOP mode release signal input Port P2 P27 to P20 8 Input output Also used as the UART input output the serial interface input output and the ...

Page 104: ...for reading input data When a port is set to the input mode the current port input status can be read by reading PxPRD PxCR register This register switches a port between input and output A port can be switched between the input mode and the output mode PxFC register This register enables the secondary function output of each port The secondary function output of each port can be enabled or disabl...

Page 105: ... 1 P10 Port output 1 Note 1 P13 INT1 input 0 P12 INT0 input 0 P11 INT5 input 0 P11 STOP input 0 P10 RESET input Note 1 Port P2 P27 to P20 Port input 0 Port output 1 0 P25 SCLK0 input 0 SERSEL SRSEL0 01 SCLK0 output 1 1 SERSEL SRSEL0 01 P24 SCL0 input output 1 Without register 1 SERSEL SRSEL0 0 SI input 0 SERSEL SRSEL0 01 P23 SDA0 input output 1 Without register 1 SERSEL SRSEL0 0 SO output 1 1 SERS...

Page 106: ...I7 to KWI4 KWUCR1 KWI3 to KWI0 KWUCR0 Port P7 P77 to P70 Port input 0 Without register Port output 1 0 P77 INT4 input 0 Without register P76 INT3 input 0 Without register P75 INT2 input 0 Without register P74 DVO output 1 1 P73 TCA1 input 0 PPGA1 output 1 1 P72 TCA0 input 0 SERSEL TCA0SEL 00 PPGA0 output 1 1 P71 TC01 input 0 PPG01 PWM01 output 1 1 P70 TC00 input 0 PPG00 PWM00 output 1 1 Table 8 2 ...

Page 107: ... input 0 0 UATCNG UAT1IO 1 Port PB PB7 to PB4 Port input 0 Port output 1 0 PB6 SCLK0 input 0 SERSEL SRSEL0 10 SERSEL SRSEL2 1 SCLK0 output 1 1 SERSEL SRSEL0 10 SERSEL SRSEL2 1 PB5 RXD0 input 0 SERSEL SRSEL0 0 SERSEL SRSEL2 1 UATCNG UAT0IO 0 TXD0 output 1 1 SERSEL SRSEL0 0 SERSEL SRSEL2 1 UATCNG UAT0IO 1 SI0 input 0 SERSEL SRSEL0 10 SERSEL SRSEL2 1 PB4 TXD0 output 1 1 SERSEL SRSEL0 0 SERSEL SRSEL2 ...

Page 108: ...Port P0 P03 P02 P01 P00 Secondary function XTOUT XTIN XOUT XIN Output latch for each bit P0DR0 write P00 XIN R Note1 R 100Ω typ Note2 Rf 1 2MΩ typ Note3 Ro 0 5kΩ typ Note4 RIN3 50kΩ typ P0PRD0 read Function control for each bit Input output control for each bit P0FC0 write P0CR0 write VDD VDD Pull up control for each bit P0PU0 write SYSCR2 XEN P0DR1 write P01 XOUT R RIN3 RIN3 Rf Ro P0PRD1 read Sys...

Page 109: ...CR2 write VDD VDD Pull up control for each bit P0PU2 write SYSCR2 XTEN Output latch for each bit P0DR3 write P03 XTOUT R RIN3 RIN3 P0PRD3 read Input output control for each bit P0CR3 write Programmable pull up resistor Programmable pull up resistor VDD VDD Pull up control for each bit P0PU3 write SYSCR1 STOP SYSCR1 OUTEN Reset signal Note1 R 100Ω typ Note2 Rf 6MΩ typ Note3 Ro 220kΩ typ Note4 RIN3 ...

Page 110: ...0 0 0 0 0 0 0 0 Function 0 Input mode port input 1 Output mode port output Port P0 function control P0FC 0x0F34 7 6 5 4 3 2 1 0 Bit Symbol P0FC2 P0FC0 Read Write R R R R R R W R R W After reset 0 0 0 0 0 0 0 1 Function 0 Port func tion Port func tion 1 XTIN I XIN I Port P0 built in pull up resistor control P0PU 0x0F27 7 6 5 4 3 2 1 0 Bit Symbol P0PU2 P0PU2 P0PU1 P0PU0 Read Write R R R R R W R W R ...

Page 111: ...1 Don t care Note 2 j 2 3 Table 8 4 P0PRD Read Value P00 to P01 Set condition P0PRDi read value P0FC0 P0CRi 1 0 1 0 0 0 Contents of port Table 8 5 P0PRD Read Value P02 to P03 Set condition P0PRDj read value P0FC2 P0CRj 1 0 1 0 0 0 Contents of port ...

Page 112: ... the STOP mode release signal input and the external reset input Port P1 contains a programmable pull up resistor on the VDD side This pull up resistor can be used when the port is used in the input mode After reset pin P10 serves as the external reset input To use pin P10 as a port refer to How to use external reset input pin as a port Table 8 6 Port P1 P13 P12 P11 P10 Secondary function INT1 INT...

Page 113: ...R write SYSCR1 STOP SYSCR3 RSTDIS SYSCR4 B2H write SYSCR1 OUTEN Reset signal Reset signal P1i R Note1 R 100Ω typ Note2 RIN3 50kΩ typ Note3 i 1 3 INT0 INT1 INT5 STOP P1PRD read In case of P11 In case of P12 and P13 Input output control for each bit P1CR write Programmable pull up resistor VDD VDD Pull up control for each bit P1PU write Interrupt STOP control Peripheral functions Low voltage detecti...

Page 114: ...I 1 Output mode port output Port P1 built in pull up resistor control P1PU 0x0F28 7 6 5 4 3 2 1 0 Bit Symbol P1PU4 P1PU2 P1PU1 P1PU0 Read Write R R R R R W R W R W R W After reset 0 0 0 0 0 0 0 0 Function 0 The built in pull up resistor is not connected 1 The built in pull up resistor is connected The resistor is connected only when the port is used in the input mode or as the open drain output Un...

Page 115: ... selected Port P2 contains a programmable pull up resistor on the VDD side This pull up resistor can be used when the port is used in the input mode or as a sink open drain output When this port is used as the serial bus interface the serial interface or the UART setting for serial interface selecting function is also needed For details refer to 8 4 Serial Interface Selecting Function For the on c...

Page 116: ...h bit P2FC write P2CR write Output control for each bit P2OUTCR write Programmable pull up resistor VDD VDD Pull up control for each bit P2PU write I n t e r n a l d a t a b u s 0 1 S Output latch for each bit P2DR write P2j R Note1 R 100Ω typ Note2 j 3 4 SCL0 SDA0 SO0 SCL0 SDA0 SI0 P2PRD read Function control for each bit Input output control for each bit P2FC write P2CR write SYSCR1 STOP SYSCR1 ...

Page 117: ...P2CR5 P2CR4 P2CR3 P2CR2 P2CR1 P2CR0 Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Function 0 Input mode port input SCLK0 I SI0 I SCLK0 I RXD0 I SI0 I RXD0 I 1 Output mode port output SCLK0 O SCL0 I O SDA0 I O SO O SCLK0 O TXD0 O TXD0 O SO0 O Port P2 function control P2FC 0x0F36 7 6 5 4 3 2 1 0 Bit Symbol P2FC5 P2FC4 P2FC3 P2FC2 P2FC1 P2FC0 Read Write R R R W R W R W R W R ...

Page 118: ...lt in pull up resistor is connected The resistor is connected only when the port is used in the input mode or as the open drain output Under any other con ditions setting to 1 does not make the resistor connected Port P2 input data P2PRD 0x000F 7 6 5 4 3 2 1 0 Bit Symbol P2PRD7 P2PRD6 P2PRD5 P2PRD4 P2PRD3 P2PRD2 P2PRD1 P2PRD0 Read Write R R R R R R R R After reset Function If the port is used in t...

Page 119: ... P4 P47 P46 P45 P44 P43 P42 P41 P40 Secondary function AIN7 KWI7 AIN6 KWI6 AIN5 KWI5 AIN4 KWI4 AIN3 KWI3 AIN2 KWI2 AIN1 KWI1 AIN0 KWI0 I n t e r n a l d a t a b u s Output latch for each bit P4DR write P4i R RIN3 Note1 R 100Ω typ Note2 RIN3 50kΩ typ Note3 i 0 to 7 KWIi Key on wakeup AD Peripheral functions P4PRD read AINi enable signal KWIi enable signal ADCCR1 AINEN Function control for each bit ...

Page 120: ...Output mode port output Port P4 function control P4FC 0x0F38 7 6 5 4 3 2 1 0 Bit Symbol P4FC7 P4FC6 P4FC5 P4FC4 P4FC3 P4FC2 P4FC1 P4FC0 Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Function 0 Port function 1 AIN7 I AIN6 I AIN5 I AIN4 I AIN3 I AIN2 I AIN1 I AIN0 I Port P4 built in pull up resistor control P4PU 0x0F2B 7 6 5 4 3 2 1 0 Bit Symbol P4PU7 P4PU6 P4PU5 P4PU4 P4PU3...

Page 121: ...TMP89FM42 Note 1 Don t care Note 2 i 0 to 7 Table 8 11 P4PRD Read Value Set condition P4PRDi read value P4CRi P4FCi 0 0 Contents of port 1 0 1 0 ...

Page 122: ...3 INT2 DVO PPGA1 TCA1 PPGA0 TCA0 PPG01 PWM01 TC01 PPG00 PWM00 TC00 I n t e r n a l d a t a b u s 0 1 S Output latch for each bit P7DR write P7i R Note1 R 100Ω typ Note2 i 0 to 7 DVO PPGA1 PPGA0 PPG01 PPG00 PWM01 PWM00 INT4 INT3 INT2 TCA1 TCA0 TC01 TC00 P7PRD read Function control for each bit Input output control for each bit P7FC write P7CR write VDD Functions enclosed by the dotted line are for ...

Page 123: ...er reset 0 0 0 0 0 0 0 0 Function 0 Input mode port input INT4 I INT3 I INT2 I TCA1 I TCA0 I TC01 I TC00 I 1 Output mode port output DVO O PPGA1 O PPGA0 O PPG01 O PWM01 O PPG00 O PWM00 O Port P7 function control P7FC 0x0F3B 7 6 5 4 3 2 1 0 Bit Symbol P7FC3 P7FC3 P7FC2 P7FC1 P7FC0 Read Write R R R R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Function 0 Port function 1 DVO O PPGA1 O PPGA0 O PPG01...

Page 124: ... 14 Port P8 P81 P80 Secondary function PPG03 PWM03 TC03 PPG02 PWM02 TC02 I n t e r n a l d a t a b u s 0 1 S Output latch for each bit P8DR write P8i R Note1 R 100Ω typ PPG03 PPG02 PWM03 PWM02 TC03 TC02 P8PRD read Function control for each bit Input output control for each bit P8FC write P8CR write VDD Functions enclosed by the dotted line are for P81 and P80 only TC03 TC02 Peripheral functions SY...

Page 125: ...r reset 0 0 0 0 0 0 0 0 Function 0 Input mode port input TC03 I TC02 I 1 Output mode port output PPG03 O PWM03 O PPG02 O PWM02 O Port P8 function control P8FC 0x0F3C 7 6 5 4 3 2 1 0 Bit Symbol P8FC1 P8FC0 Read Write R R R R R R R W R W After reset 0 0 0 0 0 0 0 0 Function 0 Port function 1 PPG03 O PWM03 O PPG02 O PWM02 O Port P8 input data P8PRD 0x0015 7 6 5 4 3 2 1 0 Bit Symbol P8PRD1 P8PRD0 Read...

Page 126: ...8 I O Ports 8 3 I O Port Registers TMP89FM42 Note 2 i 0 to 1 ...

Page 127: ...en this port is used as the UART setting for the serial interface selecting function is also needed For details refer to 8 4 Serial Interface Selecting Function Figure 8 9 Port P9 Table 8 16 Port P9 P91 P90 Secondary function RXD1 TXD1 TXD1 RXD1 I n t e r n a l d a t a b u s 0 1 S Output latch for each bit P9DR write P9i R RIN3 Note1 R 100Ω typ Note2 RIN3 50kΩ typ Note3 i 0 to 1 TXD1 RXD1 P9PRD re...

Page 128: ...n settings of P9OUTCR and P9PU Port P9 input output control P9CR 0x0F23 7 6 5 4 3 2 1 0 Bit Symbol P9CR1 P9CR0 Read Write R R R R R R R W R W After reset 0 0 0 0 0 0 0 0 Function 0 Input mode port input RXD1 I RXD1 I 1 Output mode port output TXD1 O TXD1 O Port P9 function control P9FC 0x0F3D 7 6 5 4 3 2 1 0 Bit Symbol P9FC1 P9FC0 Read Write R R R R R R R W R W After reset 0 0 0 0 0 0 0 0 Function...

Page 129: ... P9PRD0 Read Write R R R R R R R R After reset 0 0 0 0 0 0 Function If the port is used in the input mode or as the sink open drain output the contents of the port are read If not 0 is read Table 8 17 P9PRD Read Value Set condition P9PRDi read value P9CRi P9OUTCRi 0 Contents of port 1 0 0 1 1 Contents of port ...

Page 130: ...erial interface selecting function is also needed For details refer to 8 4 Serial Interface Selecting Function Figure 8 10 Port PB Table 8 18 Port PB PB7 PB6 PB5 PB4 Secondary function SCLK0 SI0 RXD0 TXD0 SO0 TXD0 RXD0 I n t e r n a l d a t a b u s 0 1 S Output latch for each bit PBDR write PBi R Note1 R 100Ω typ Note2 Nch large current Peripheral functions PBPRD read Function control for each bit...

Page 131: ... port output Port PB function control PBFC 0x0F3F 7 6 5 4 3 2 1 0 Bit Symbol PBFC6 PBFC5 PBFC4 Read Write R R W R W R W R R R R After reset 0 0 0 0 0 0 0 0 Function 0 Port function 1 SCLK0 O TXD0 O TXD0 O SO0 O Port PB output control PBOUTCR 0x0F4C 7 6 5 4 3 2 1 0 Bit Symbol PBOUT7 PBOUT6 PBOUT5 PBOUT4 Read Write R W R W R W R W R R R R After reset 0 0 0 0 0 0 0 0 Function 0 C MOS output 1 Open dr...

Page 132: ...8 I O Ports 8 3 I O Port Registers TMP89FM42 Note 1 Don t care Note 2 i 4 to 7 Table 8 19 PBPRD Read Value Set condition PBPRDi read value PBCRi PBOUTCRi 0 Contents of port 1 0 0 1 1 Contents of port ...

Page 133: ...may receive transmit unexpected data and operate improperly Serial interface selection control register SERSEL 0x0FCB 7 6 5 4 3 2 1 0 Bit Symbol TCA0SEL SRSEL2 SRSEL0 Read Write R W R W R R W R R R W R W After reset 0 0 0 0 0 0 0 0 TCA0SEL 16 bit timer counter A0 input switch ing 00 01 10 11 P72 input TCA0 P21 input also used as RXD0 P91 input also used as RXD1 Reserved SRSEL2 Select UART0 SIO0 in...

Page 134: ... R R R R R W R W After reset 0 0 0 0 0 0 0 0 RXD pin TXD pin UAT1IO Select UART1 input output port 0 1 P91 P90 P90 P91 UAT0IO Select UART0 input output port SERSEL SERSEL2 0 SERSEL SERSEL2 1 SERSEL SERSEL2 0 SERSEL SERSEL2 1 0 1 P21 P20 PB5 PB4 P20 P21 PB4 PB5 Table 8 20 Select input output port and interrupt SERSEL SRSEL0 SERSEL SRSEL2 UATCNG UAT0IO Port Interrupt UART0 SIO0 I2C0 SIO0 PB4 PB5 PB6...

Page 135: ...n about SIO1 and UART1 Figure 8 17 Serial Interface Selecting Function Added PB Port Deleted P92 and P94 Ports Deleted SIO1 Serial interface selection control register Deleted SRSEL1 Revised SRSEL2 description from output to input output Deleted Table 8 20 RA003 Figure 8 2 Port P0 P00 P01 Figure 8 3 Port P0 P02 P03 Added damping resistor Ro Figure 8 4 Port P1 Deleted STOP control from P11 pin inpu...

Page 136: ...8 I O Ports 8 5 Revision History TMP89FM42 ...

Page 137: ...023 SBI0CR2 SBI0SR2 0x0004 P4DR 0x0024 I2C0AR 0x0005 Reserved 0x0025 SBI0DBR 0x0006 Reserved 0x0026 T00REG 0x0007 P7DR 0x0027 T01REG 0x0008 P8DR 0x0028 T00PWM 0x0009 P9DR 0x0029 T01PWM 0x000A Reserved 0x002A T00MOD 0x000B PBDR 0x002B T01MOD 0x000C Reserved 0x002C T001CR 0x000D P0PRD 0x002D TA0DRAL 0x000E P1PRD 0x002E TA0DRAH 0x000F P2PRD 0x002F TA0DRBL 0x0010 Reserved 0x0030 TA0DRBH 0x0011 P4PRD 0...

Page 138: ...d 0x0F2C Reserved 0x0F4C PBOUTCR 0x0F6C Reserved 0x0F0D Reserved 0x0F2D Reserved 0x0F4D Reserved 0x0F6D Reserved 0x0F0E Reserved 0x0F2E Reserved 0x0F4E Reserved 0x0F6E Reserved 0x0F0F Reserved 0x0F2F Reserved 0x0F4F Reserved 0x0F6F Reserved 0x0F10 Reserved 0x0F30 P9PU 0x0F50 Reserved 0x0F70 Reserved 0x0F11 Reserved 0x0F31 Reserved 0x0F51 Reserved 0x0F71 Reserved 0x0F12 Reserved 0x0F32 Reserved 0x0...

Page 139: ...d 0x0F8D T03MOD 0x0FAD TA1CR 0x0FCD WUCCR 0x0FED Reserved 0x0F8E T023CR 0x0FAE TA1SR 0x0FCE WUCDR 0x0FEE Reserved 0x0F8F Reserved 0x0FAF Reserved 0x0FCF CGCR 0x0FEF Reserved 0x0F90 Reserved 0x0FB0 Reserved 0x0FD0 FLSCR1 0x0FF0 ILPRS1 0x0F91 Reserved 0x0FB1 Reserved 0x0FD1 FLSCR2 FLSCRM 0x0FF1 ILPRS2 0x0F92 Reserved 0x0FB2 Reserved 0x0FD2 FLSSTB 0x0FF2 ILPRS3 0x0F93 Reserved 0x0FB3 Reserved 0x0FD3 ...

Page 140: ...C Reserved 0x0E8C Reserved 0x0EAC Reserved 0x0E4D Reserved 0x0E6D Reserved 0x0E8D Reserved 0x0EAD Reserved 0x0E4E Reserved 0x0E6E Reserved 0x0E8E Reserved 0x0EAE Reserved 0x0E4F Reserved 0x0E6F Reserved 0x0E8F Reserved 0x0EAF Reserved 0x0E50 Reserved 0x0E70 Reserved 0x0E90 Reserved 0x0EB0 Reserved 0x0E51 Reserved 0x0E71 Reserved 0x0E91 Reserved 0x0EB1 Reserved 0x0E52 Reserved 0x0E72 Reserved 0x0E9...

Page 141: ...d 0x0EC5 Reserved 0x0ED5 Reserved 0x0EE5 Reserved 0x0EF5 Reserved 0x0EC6 Reserved 0x0ED6 Reserved 0x0EE6 Reserved 0x0EF6 Reserved 0x0EC7 Reserved 0x0ED7 Reserved 0x0EE7 Reserved 0x0EF7 Reserved 0x0EC8 Reserved 0x0ED8 Reserved 0x0EE8 Reserved 0x0EF8 Reserved 0x0EC9 Reserved 0x0ED9 Reserved 0x0EE9 Reserved 0x0EF9 Reserved 0x0ECA Reserved 0x0EDA Reserved 0x0EEA Reserved 0x0EFA Reserved 0x0ECB Reserve...

Page 142: ...9 Special Function Registers 9 3 SFR3 0x0E40 to 0x0EFF TMP89FM42 ...

Page 143: ...to each peripheral function is enabled and the function becomes available by setting the cor responding bit of the low power consumption registers POFFCRn to 1 After reset the low power consumption registers POFFCRn are initialized to 0 and thus the peripheral func tions are unavailable When each peripheral function is used for the first time be sure to set the corresponding bit of the low power c...

Page 144: ...ble Low power consumption register 1 POFFCR1 7 6 5 4 3 2 1 0 0x0F75 Bit Symbol SBI0EN UART1EN UART0EN Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 SBI0EN I2C0 control 0 1 Disable Enable UART1EN UART1 control 0 1 Disable Enable UART0EN UART0 control 0 1 Disable Enable Low power consumption register 2 POFFCR2 7 6 5 4 3 2 1 0 0x0F76 Bit Symbol RTCEN SIO0EN Read Write R W R W...

Page 145: ... control 0 1 Disable Enable INT4EN INT4 control 0 1 Disable Enable INT3EN INT3 control 0 1 Disable Enable INT2EN INT2 control 0 1 Disable Enable INT1EN INT1 control 0 1 Disable Enable INT0EN INT0 control 0 1 Disable Enable ...

Page 146: ...10 Low Power Consumption Function for Peripherals TMP89FM42 ...

Page 147: ...ncy is subject to some fluctuations to synchronize fs and fcgck Note 4 Bits 7 to 3 of DVOCR are read as 0 11 2 1 Function Select the divider output frequency at DVOCR DVOCK Divider output control register DVOCR 0x0038 7 6 5 4 3 2 1 0 Bit Symbol DV0EN DVOCK Read Write R R R R R R W R W After reset 0 0 0 0 0 0 0 0 DVOEN Enables disables the divider output 0 Disable the divider output 1 Enable the di...

Page 148: ...P or IDLE0 SLEEP0 mode is activated and DVOCR DVOEN is cleared to 0 the frequency of the divider output is not the frequency set at DVOCR DVOCK Figure 11 2 Divider Output Timing When the operation is changed from NORMAL mode to SLOW mode or from SLOW mode to NORMAL mode the divider output frequency does not reach the expected value due to synchronization of the gear clock fcgck and the low frequen...

Page 149: ...TMP89FM42 11 3 Revision History Rev Description RA001 Deleted SLEEP2 description ...

Page 150: ...11 Divider Output DVO 11 3 Revision History TMP89FM42 ...

Page 151: ...ead Write R R R R R W R W After reset 0 0 0 0 0 0 0 0 TBTEN Enables disables the time base timer interrupt requests 0 Disables generation of interrupt request signals 1 Enables generation of interrupt request signals TBTCK Selects the time base timer interrupt frequency Unit Hz TBTCK NORMAL 1 2 IDLE 1 2 mode SLOW1 2 SLEEP1 mode DV9CK 0 DV9CK 1 000 fcgck 222 fs 215 fs 215 001 fcgck 220 fs 213 fs 21...

Page 152: ... a time base timer interrupt request is enabled Therefore the period from when the time TBTCR TBTEN is set to 1 to the time when the first interrupt request occurs is shorter than the frequency period set at TBTCR TBTCK Figure 12 2 Time Base Timer Interrupt When the operation is changed from NORMAL mode to SLOW mode or from SLOW mode to NORMAL mode The interrupt request will not occur at the expec...

Page 153: ...TMP89FM42 DI IMF 0 SET EIRL 5 Set the interrupt enable register EI IMF 1 LD TBTCR 0y00000010 Set the interrupt frequency LD TBTCR 0y00001010 Enable generation of interrupt request signals ...

Page 154: ...12 Time Base Timer TBT 12 2 Revision History TMP89FM42 12 2 Revision History Rev Description RA001 Deleted SLEEP2 description ...

Page 155: ...L Address TAxDRAH Address TAxDRBL Address TAxDRBH Address TAxMOD Address TAxCR Address TAxSR Address Low power consump tion register Timer counter A0 TA0DRAL 0x002D TA0DRAH 0x002E TA0DRBL 0x002F TA0DRBH 0x0030 TA0MOD 0x0031 TA0CR 0x0032 TA0SR 0x0033 POFFCR0 TCA0EN Timer counter A1 TA1DRAL 0x0FA8 TA1DRAH 0x0FA9 TA1DRBL 0x0FAA TA1DRBH 0x0FAB TA1MOD 0x0FAC TA1CR 0x0FAD TA1SR 0x0FAE POFFCR0 TCA1EN Tab...

Page 156: ...dge detection 2 Edge detection 1 Edge detection 1 Edge detection 2 Edge detection 2 Rising Falling Edge detection 1 Falling Rising TA0TED 0 1 Edge detection 1 Edge detection 2 TAMCAP EN TA0CAP TA0NC fcgck 2 10 or fs 2 3 fcgck 2 6 fcgck 2 2 fcgck 2 E A B C D 0 1 2 TA0CK TA0M TA0DBE TA0TED TA0METT TA0NC TA0OVE TA0CAP TA0MPPG TA0CPFB TA0CPFA TA0OVF TA0S TA0TFF Y Y S0 S1 S Selector Selector Selector W...

Page 157: ...d two 16 bit timer A0 registers TA0DRA and TA0DRB Low power consumption register 0 POFFCR0 7 6 5 4 3 2 1 0 0x0F74 Bit Symbol TC023EN TC001EN TCA1EN TCA0EN Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 TC023EN TC02 03 control 0 1 Disable Enable TC001EN TC00 01 control 0 1 Disable Enable TCA1EN TCA1 control 0 1 Disable Enable TCA0EN TCA0 control 0 1 Disable Enable ...

Page 158: ...ternal trigger input selection 0 1 Rising edge H level Falling edge L level TA0MCAP Pulse width measurement mode control 0 1 Double edge capture Single edge capture TA0METT External trigger timer mode control 0 1 Trigger start Trigger start stop TA0CK Timer counter 1 source clock selection NORMAL 1 2 or IDLE 1 2 mode SLOW1 2 or SLEEP1 mode SYSCR1 DV9CK 0 SYSCR1 DV9CK 1 00 fcgck 210 fs 23 fs 23 01 ...

Page 159: ...nceller and no signal is input to the timer Timer counter A0 control register TA0CR 7 6 5 4 3 2 1 0 0x0032 Bit Symbol TA0OVE TA0TFF TA0NC TA0CAP TA0MPPG TA0S Read Write R W R W R W R R R W R W After reset 0 1 0 0 0 0 0 0 TA0OVE Overflow interrupt control 0 1 Generate no INTTA0 interrupt request when the counter overflow occurs Generate an INTTA0 interrupt request when the counter overflow occurs T...

Page 160: ... 0 0x0033 Bit Symbol TA0OVF TA0CPFA TA0CPFB Read Write R R R R R R R R After reset 0 0 0 0 0 0 0 0 TA0OVF Overflow flag 0 1 No overflow has occurred At least an overflow has occurred TA0CPFA Capture completion flag A 0 1 No capture operation has been executed At least a pulse width capture has been executed in the double edge capture TA0CPFB Capture completion flag B 0 1 No capture operation has b...

Page 161: ...the timer unusable Setting POFFCR0 TCA0EN to 1 enables the basic clock supply to timer counter A0 and allows the timer to operate After reset POFFCR0 TCA0EN is initialized to 0 and this makes the timer unusable When using the timer for the first time be sure to set POFFCR0 TCA0EN to 1 in the initial setting of the program before the timer control register is operated Do not change POFFCR0 TCA0EN t...

Page 162: ...nting and be cleared to 0000H 13 4 1 3 Auto capture The latest contents of the up counter can be taken into timer register B TA0DRB by setting TA0CR TA0ACAP to 1 auto capture function When TA0CR TA0ACAP is 1 the current con tents of the up counter can be read by reading TA0DRBL TA0DRBH is loaded at the same time as TA0DRBL is read Therefore when reading the captured value be sure to read TA0DRBL a...

Page 163: ...ation the set value is first stored into the double buffer and TA0DRAH L are not updated immediately TA0DRAH L compare the up counter value to the last set values If the values are matched an INTTCA0 interrupt request is generated and the double buffer set value is stored in TA0DRAH L Subsequently the match detection is executed using a new set value When a read instruction is executed on TA0DRAH ...

Page 164: ...CA interrupt request 2 3 4 mn 1 mn 0 1 rs 0 1 2 2 0 3 TA0DRAH TA0CR TA0S s r Timer stop Match detection Counter clear rs 1 TA0MOD TA0DBE When the double buffer is disabled TA0MOD TA0DBE 0 Source clock Counter Timer start 1 0 n m Write to TA0DRAL Write to TA0DRAH TA0DRAL Match detection Write n Write s Write m Write r Counter clear INTTCA interrupt request 2 3 4 mn 1 mn 0 1 mn 0 1 2 3 TA0DRAH TA0CR...

Page 165: ...A0DRBL is read Read TA0DRBL Read TA0DRBH Read value 00H Read value 00H TA0DRBL TA0DRBH TA0CR TA0S Timer stop 18FD 0000 0001 0002 18FE 18FF 1900 1901 1902 1903 1904 1905 1906 0000 FD 00 01 00 18 02 FE FF 00 01 02 03 04 05 06 00 00 TA0MOD TA0ACAP Read value FEH Read value 18H Read value 00H Read value 00H Read value 18H ...

Page 166: ...ut to the TCA0 pin the up counter incre ments according to the selected source clock When a match between the up counter value and the value set to timer register A TA0DRA is detected an INTTA0 interrupt request is generated and the up counter is cleared to 0000H After being cleared the up counter continues counting When TA0MOD TA0METT is 1 and the edge opposite to the selected trigger edge is det...

Page 167: ... detection Counter clear rs 1 TA0MOD TA0TED TA0 pin input When the trigger is started TA0MOD TA0METT 0 Timer start Counting start Counting start Counting start Counting stop 1 0 n m TA0DRAL Match detection Write n Write s Write m Write r Reflected by writing to TA0DRAH Reflected by writing to TA0DRAH Counter clear Counter clear INTTCA interrupt request 2 3 mn 1 mn 0 1 rs 0 1 1 2 0 0 TA0DRAH TA0CR ...

Page 168: ...equired mode settings before starting the timer 13 4 3 2 Operation After the event counter mode is started when the selected trigger edge is input to the TCA0 pin the up counter increments When a match between the up counter value and the value set to timer register A TA0DRA is detected an INTTA0 interrupt request is generated and the up counter is cleared to 0000H After being cleared the up count...

Page 169: ... TA0MOD TA0TED 0 1 0 n m Write to TA0DRAL Write to TA0DRAH TA0DRAL Match detection Write n Write s Write m Write r Reflected by writing to TA0DRAH Reflected by writing to TA0DRAH Counter clear INTTCA interrupt request 2 3 4 mn 1 mn 0 1 rs 0 1 2 2 0 3 TA0DRAH TA0CR TA0S s r Timer stop Match detection Counter clear rs 1 ...

Page 170: ...o 1 After the timer is started writing to TA0MOD and TA0CR TA0OVE is disabled Be sure to complete the required mode settings before starting the timer 13 4 4 2 Operation After the operation is started when the level selected at TA0MOD TA0TED is input to the TCA0 pin the up counter increments according to the source clock selected at TA0MOD TA0CK When a match between the up counter value and the va...

Page 171: ...nt in the period of H level 1 0 n m Write to TA0DRAL Write to TA0DRAH TA0DRAL Match detection Write n Write m Reflected by writing to TA0DRAH Counter clear INTTCA interrupt request 2 5 4 6 4 5 6 3 mn 1 mn 1 0 2 0 3 TA0DRAH TA0CR TA0S Timer stop TA0MOD TA0TED TA0 pin input During the H level counting TA0MOD TA0TED 0 ...

Page 172: ...TA0CR TA0S to 1 After the timer is started writing to TA0MOD and TA0CR TA0OVE is disabled Be sure to complete the required mode settings before starting the timer 13 4 5 2 Operation After the timer is started when the selected trigger edge start edge is input to the TCA0 pin the up counter increments according to the selected source clock Subsequently when the edge opposite to the selected edge is...

Page 173: ...apture starts when the selected trigger edge is detected next Figure 13 7 Pulse Width Measurement Mode Timing Chart Source clock Counter Counter clear Counter clear Counter clear Counter clear Timer start Count start Count start After the timer is started if the falling edge is detected first no interrupt occurs 1 0 TA0DRBH L INTTCA interrupt request 0 2 4 3 3 mn 1 mn 1 0 mn 2 0 TA0CR TA0S Timer s...

Page 174: ...ntinues counting When a match between the up counter value and the value set to timer register A TA0DRA is detected the PPGA0 pin is changed to the L level if TA0CR TA0TEFF is 0 or the PPGA0 pin is changed to the H level if TA0CR TA0TFF is 1 At this time an INTTA0 interrupt request occurs If the PPG output control TA0CR TA0MPPG is set to 1 one shot TA0CR TA0S is automatically cleared to 0 and the ...

Page 175: ...tion the set value is first stored into the double buffer and TA0DRAH L are not updated immediately TA0DRAH L TA0DRBH L compare the last set values to the counter value If a match is detected an INTTCA0 interrupt request is generated and the double buffer set value is stored into TA0DRAH L TA0DRBH L Subsequently the match detection is exe cuted using a new set value When a read instruction is exec...

Page 176: ...r INTTCA interrupt request 2 m 1 m 1 n 0 0 TA0DRBL H TA0CR TA0S Timer stop Match detection Match detection Counter clear 2 r 1 r 1 r r 1 s 0 Match detection TA0MOD TA0TFF PPG0 pin output Continuous TA0CR TA0MPPG 0 Double buffer TA0MOD TA0DBE 1 r Duty pulse Source clock Counter Timer start 1 0 n m n 1 cycle Write to TA0DRAL H Write to TA0DRBL H TA0DRAL H Match detection Match detection Write n Writ...

Page 177: ...after a period of time that is equal to four times the sampling interval after TA0CR TA0NC is set has elapsed This stabilizes the input signal Set TA0CR TA0NC while the timer is stopped TA0CR TA0S 0 When TA0CR TA0S is 1 writing is ignored In the SLOW 1 2 or SLEEP 1 mode setting TA0CR TA0NC to 11 selects fs 2 as the source clock for the operation Setting TA0CR TA0NC to 00 disables the noise cancell...

Page 178: ...it Timer Counter TCA 13 6 Revision History TMP89FM42 13 6 Revision History Rev Description RA001 Table 13 3 Timer Mode Resolution and Maximum Time Setting Revised Resolution and Maximum time of TA0MOD TA0CK 11 ...

Page 179: ...gnment 16 bit mode T0xREG Address T0xPWM Address T0xMOD Address T0xxCR Address Low power consumption register Timer counter 00 Lower T00REG 0x0026 T00PWM 0x0028 T00MOD 0x002A T001CR 0x002C POFFCR0 TC001EN Timer counter 01 Higher T01REG 0x0027 T01PWM 0x0029 T01MOD 0x002B Timer counter 02 Lower T02REG 0x0F88 T02PWM 0x0F8A T02MOD 0x0F8C T023CR 0x0F8E POFFCR0 TC023EN Timer counter 03 Higher T03REG 0x0...

Page 180: ...p Clear Overflow Timer event count modes 8 16 bit PPG mode Reading and writing of T00REG Reading and writing of T00PWM T00PWM Double buffer Double buffer Double buffer Double buffer 0 1 0 0 0 1 1 1 INTT01 interrupt request PPG1 PWM1 pin output TFF1 Internal bus T01MOD T001CR 2 TCK1 EIN1 TFF0 TCM0 DBE0 DBE1 TCM1 TFF1 OUTAND TCAS TC00RUN TC01RUN T00MOD TCK0 EIN0 2 2 2 TC00 pin input fcgck 2 11 or fs...

Page 181: ...figuration of T00PWM in the 8 bit and 12 bit PWM modes refer to 14 4 3 8 bit pulse width modulation PWM output mode and 14 4 7 12 bit pulse width modulation PWM output mode Timer register 00 T00REG 15 14 13 12 11 10 9 8 0x0026 Bit Symbol T00REG Read Write R W After reset 1 1 1 1 1 1 1 1 Timer register 00 T00PWM 7 6 5 4 3 2 1 0 0x0028 Bit Symbol T00PWM Read Write R W After reset 1 1 1 1 1 1 1 1 ...

Page 182: ...AS the timer start is controlled at T001CR T01RUN Timer 00 is not started by writing data into T001CR T00RUN Timer counter 00 mode register T00MOD 7 6 5 4 3 2 1 0 0x002A Bit Symbol TFF0 DBE0 TCK0 EIN0 TCM0 Read Write R W R W R W R W R W After reset 1 1 0 0 0 0 0 0 TFF0 Timer F F0 control 0 1 Clear Set DBE0 Double buffer control 0 1 Disable the double buffer Enable the double buffer TCK0 Operation ...

Page 183: ...of T00PWM in the 8 bit and 12 bit PWM modes refer to 14 4 3 8 bit pulse width modulation PWM output mode and 14 4 7 12 bit pulse width modulation PWM output mode Timer register 01 T01REG 15 14 13 12 11 10 9 8 0x0027 Bit Symbol T01REG Read Write R W After reset 1 1 1 1 1 1 1 1 Timer register 01 T01PWM 7 6 5 4 3 2 1 0 0x0029 Bit Symbol T01PWM Read Write R W After reset 1 1 1 1 1 1 1 1 ...

Page 184: ...trol 0 1 Disable the double buffer Enable the double buffer TCK1 Operation clock selection NORMAL1 2 or IDLE1 2 mode SLOW1 2 or SLEEP1 mode SYSCR1 DV9CK 0 SYSCR1 DV9CK 1 000 fcgck 211 fs 24 fs 24 001 fcgck 210 fs 23 fs 23 010 fcgck 28 fcgck 28 011 fcgck 26 fcgck 26 100 fcgck 24 fcgck 24 101 fcgck 22 fcgck 22 110 fcgck 2 fcgck 2 111 fcgck fcgck fs 22 EIN1 Selection for using external source clock 0...

Page 185: ...gisters in common Low power consumption register 0 POFFCR0 7 6 5 4 3 2 1 0 0x0F74 Bit Symbol TC023EN TC001EN TCA1EN TCA0EN Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 TC023EN TC02 03 control 0 1 Disable Enable TC001EN TC00 01 control 0 1 Disable Enable TCA1EN TCA1 control 0 1 Disable Enable TCA0EN TCA0 control 0 1 Disable Enable ...

Page 186: ...in unchanged by executing write instructions on OUTAND and TCAS OUTAND and TCAS can be changed at the same time as TC01RUN and TC00RUN are changed from 0 to 1 Timer counter 01 control register T001CR 7 6 5 4 3 2 1 0 0x002C Bit Symbol OUTAND TCAS T01RUN T00RUN Read Write R R R R R W R W R W R W After reset 0 0 0 0 0 0 0 0 OUTAND Timers 00 and 01 output control 0 1 Output the timer 00 output from th...

Page 187: ...e TCK1 Note 3 i 0 1 i 0 only in the 16 bit modes Table 14 3 Operation Modes and Usable Source Clocks NORMAL1 2 and IDLE1 2 modes TCK0 000 001 010 011 100 101 110 111 TC0i pin input Operation mode fcgck 211 or fs 24 fcgck 210 or fs 23 fcgck 28 fcgck 26 fcgck 24 fcgck 22 fcgck 2 fcgck 8 bit timer modes 8 bit timer Ο Ο Ο Ο Ο Ο Ο Ο 8 bit event counter Ο 8 bit PWM Ο Ο Ο Ο Ο Ο Ο Ο 8 bit PPG Ο Ο Ο Ο Ο Ο ...

Page 188: ...ders the timers unusable Setting POFFCR0 TC001EN to 1 enables the basic clock supply to timer counters 00 and 01 and allows the timers to operate After reset POFFCR0 TC001EN are initialized to 0 and this makes the timers unusable When using the tim ers for the first time be sure to set POFFCR0 TC001EN to 1 in the initial setting of the program before the timer control registers are operated Do not...

Page 189: ...er 14 4 1 2 Operation Setting T001CR T00RUN to 1 allows the 8 bit up counter to increment based on the selected inter nal source clock When a match between the up counter value and the T00REG set value is detected an INTT00 interrupt request is generated and the up counter is cleared to 0x00 After being cleared the up counter restarts counting Setting T001CR T00RUN to 0 during the timer operation ...

Page 190: ...e Resolution and Maximum Time Setting T00MOD TCK0 Source clock Hz Resolution Maximum time setting NORMAL1 2 or IDLE1 2 mode SLOW1 2 or SLEEP1 mode fcgck 10MHz fs 32 768KHz fcgck 10MHz fs 32 768KHz SYSCR1 DV9CK 0 SYSCR1 DV9CK 1 000 fcgck 211 fs 24 fs 24 204 8µs 488 2µs 52 2ms 124 5ms 001 fcgck 210 fs 23 fs 23 102 4µs 244 1µs 26 1ms 62 3ms 010 fcgck 28 fcgck 28 25 6µs 6 5ms 011 fcgck 26 fcgck 26 6 4...

Page 191: ...2 3 4 m 1 m 0 1 n 0 1 2 2 0 3 T00REG T001CR T00RUN n Timer stop Match detection Counter clear n 1 T00MOD DBE0 When the double buffer is disabled T00MOD DBE0 0 Source clock Counter Timer start 1 0 m Write to T00REG Match detection Write m Write n Counter clear INTT00 interrupt request 2 3 4 m 1 m 0 1 m 0 1 2 3 T00REG T001CR T00RUN n m Double buffer n Match detection Match detection Counter clear 0 ...

Page 192: ...e TC00 pin When a match between the up counter value and the T00REG set value is detected an INTT00 interrupt request is generated and the up counter is cleared to 0x00 After being cleared the up counter restarts counting Setting T001CR T00RUN to 0 during the timer operation makes the up counter stop counting and be cleared to 0x00 The maximum frequency to be supplied is fcgck 22 Hz in NORMAL1 2 o...

Page 193: ...the double buffer is disabled T00MOD DBE0 0 1 0 m Write to T00REG Match detection Write m Write n Reflected by writing to T00REG Reflected by writing to T00REG Counter clear INTT00 interrupt request 2 3 4 m 1 m 0 1 n 0 1 2 2 0 3 T00REG T001CR T00RUN n Timer stop Match detection Counter clear n 1 ...

Page 194: ...1 starts the operation After the timer is started writing to T00MOD becomes invalid Be sure to complete the required mode settings before starting the timer In the 8 bit PWM mode the T00PWM register is configured as follows PWMDUTY is a 7 bit register used to set the duty pulse width value the time before the first output change in a cycle 128 counts of the source clock PWMAD is a register used to...

Page 195: ...el When T00MOD TFF0 is 1 the PWM0 pin changes from the H to L level If T00PWM PWMAD is 1 an additional pulse that corresponds to 1 count of the source clock is added at the 2 n th match detection n 1 2 3 In other words the PWM0 pin output is reversed at the timing of T00PWM PWMDUTY 1 When T00MOD TFF0 is 0 the period of the L level becomes longer than the value set to T00 PWMDUTY by 1 source clock ...

Page 196: ...P7CR0 to 1 LD POFFCR0 0x10 Sets TC001EN to 1 DI Sets the interrupt master enable flag to disable SET EIRH 4 Sets the INTTC00 interrupt enable register to 1 EI Sets the interrupt master enable flag to enable LD T00MOD 0xF2 Selects the 8 bit PWM mode and fcgck 2 LD T00PWM 0x73 Sets the timer register duty pulse 11 6µs 2 2 fcgck 0x73 SET T001CR 0 Starts TC00 Source clock Counter Timer start 1 0 m m m...

Page 197: ...double buffer is disabled When a write instruction is executed on T00PWM during the timer operation the set value is immediately stored in T00PWM Subsequently the match detection is executed using a new set value If the value set to T00PWM is smaller than the up counter value the PWM0 pin is not reversed until the up counter overflows and a match detection is executed using a new set value If the ...

Page 198: ...KHz SYSCR1 DV9CK 0 SYSCR1 DV9CK 1 000 fcgck 211 fs 24 fs 24 204 8µs 488 2µs 26 2ms 52 4ms 62 5ms 125ms 001 fcgck 210 fs 23 fs 23 102 4µs 244 1µs 13 1ms 26 2ms 31 3ms 62 5ms 010 fcgck 28 fcgck 28 25 6µs 3 3ms 6 6ms 011 fcgck 26 fcgck 26 6 4µs 819 2µs 1638 4µs 100 fcgck 24 fcgck 24 1 6µs 204 8µs 409 6µs 101 fcgck 22 fcgck 22 400ns 51 2µs 102 4µs 110 fcgck 2 fcgck 2 200ns 25 6µs 51 2µs 111 fcgck fcgc...

Page 199: ...rted writing to T00MOD becomes invalid Be sure to complete the required mode settings before starting the timer Figure 14 8 PPG0 Pulse Output Set the initial state of the PPG0 pin at T00MOD TFF0 Setting T00MOD TFF0 to 0 selects the L level as the initial state of the PPG0 pin Setting T00MOD TFF0 to 1 selects the H level as the initial state of the PPG0 pin If the PPG0 pin is set as the function ou...

Page 200: ...ecuted using a new set value When a read instruction is executed on T00PWM T00REG the value in the double buffer the last set value is read out not the T00PWM T00REG value the currently effective value When a write instruction is executed on T00PWM T00REG while the timer is stopped the set value is immediately stored in both the double buffer and T00PWM T00REG When the double buffer is disabled Wh...

Page 201: ...timer is stopped Returns to the level selected at TFF0 INTT00 interrupt request 1 m 1 m 0 T00PWM T001CR T00RUN p s w Write to T00REG Double buffer Write p Write s Write w p Timer stop Match detection r 1 r 1 0 s r 1 r 1 0 s t 1 t 1 0 0 w Match detection Match detection Counter clear Counter clear Counter clear Counter clear T00MOD TFF0 PPG0 pin output When the double buffer is enabled T00MOD DBE0 ...

Page 202: ...ngs when T001CR T00RUN and T01RUN are 0 14 4 5 2 Operations Setting T001CR T01RUN to 1 allows the 16 bit up counter to increment based on the selected internal source clock When a match between the up counter value and the T00 01REG set value is detected an INTT01 interrupt request is generated and the up counter is cleared to 0x0000 After being cleared the up counter restarts counting Setting T00...

Page 203: ...REG in this order while the timer is stopped the set value is immediately stored in T01 00REG When a read instruction is executed on T01 00REG the last value written into T01 00REG is read out regardless of the T00MOD DBE1 setting Example Operate TC00 and TC01 in the 16 bit timer mode with the operation clock of fcgck 2 Hz and generate interrupts at 96 µs intervals fcgck 10 MHz LD POFFCR0 0x10 Set...

Page 204: ... 2 0 3 T001CR T01RUN Timer stop Counter clear km Write to T01REG Match detection Write k Write s Write to T01REG Write k Write s T01 00REG sr sr 1 T01MOD DBE1 When the double buffer is disabled T01MOD DBE1 0 Source clock Counter Timer start 1 0 km Write to T00REG Match detection Write m Write r Counter clear INTT01 interrupt request 2 3 4 km 1 km 0 1 km 0 1 2 3 T01 00REG T001CR T01RUN sr km Double...

Page 205: ...MHz fs 32 768KHz fcgck 10MHz fs 32 768KHz SYSCR1 DV9CK 0 SYSCR1 DV9CK 1 000 fcgck 211 fs 24 fs 24 204 8µs 488 2µs 13 4s 32s 001 fcgck 210 fs 23 fs 23 102 4µs 244 1µs 6 7s 16s 010 fcgck 28 fcgck 28 25 6µs 1 7s 011 fcgck 26 fcgck 26 6 4µs 419 4ms 100 fcgck 24 fcgck 24 1 6µs 104 9ms 101 fcgck 22 fcgck 22 400ns 26 2ms 110 fcgck 2 fcgck 2 200ns 13 1ms 111 fcgck fcgck fs 22 100ns 122 1µs 6 6ms 8s ...

Page 206: ...buffer Setting T001CR T01RUN to 1 starts the operation After the timer is started writing to T01MOD becomes invalid Be sure to complete the required mode settings before starting the timer Make settings when T001CR T00RUN and T01RUN are 0 14 4 6 2 Operations Setting T001CR T01RUN to 1 allows the 16 bit up counter to increment at the falling edge of the TC00 pin When a match between the up counter ...

Page 207: ... rs 0 1 2 2 0 3 T01 00REG T001CR T01RUN rs Timer stop Match detection Counter clear Counter clear rs 1 TC00 pin input Counter Timer start When the double buffer is enabled T01MOD DBE1 1 1 0 km Write to T00REG Match detection Write m Write s Reflected by writing to T01REG Reflected by writing to T01REG Counter clear Write to T01REG Write k Write r INTT00 interrupt request 2 3 4 km 1 km 0 1 km 0 1 2...

Page 208: ... T00PWM and T01PWM is indicated as T01 00PWM The timer register settings are reflected on the double buffer or T01 00PWM when a write instruction is executed on T01PWM Be sure to execute the write instructions on T00PWM and T01PWM in this order When data is written to the high order register the set values of the low order and high order registers become effective at the same time Bits 7 to 4 of T...

Page 209: ... value of T01MOD TFF1 is output to the PWM1 pin Table 14 11 shows the list of output levels of the PWM1 pin Table 14 10 Cycles in Which Additional Pulses Are Inserted Cycles in which additional pulses are inserted among cycles 1 to 16 PWMAD0 1 9 PWMAD1 1 5 13 PWMAD2 1 3 7 11 15 PWMAD3 1 2 4 6 8 10 12 14 16 Table 14 11 List of Output Levels of PWM1 Pin TFF1 PWM1pin output level Before the start of ...

Page 210: ... than the value set to PWMDUTY by 1 source clock This function allows 16 cycles of output pulses to be handled with a resolution nearly equivalent to 12 bits No additional pulse is inserted when PWMAD3 to 0 are all 0 Subsequently the up counter continues counting up When the up counter value reaches 256 an over flow occurs and the up counter is cleared to 0x00 At the same time the output of the PW...

Page 211: ...ored in T01 00PWM Subsequently the match detection is executed using a new set value When a read instruction is executed on T01 00PWM T00REG the value in the double buffer the last set value is read out not the T01 00PWM value the currently effective value When write instructions are executed on T00PWM and T01PWM in this order while the timer is stopped the set value is immediately stored in both ...

Page 212: ... 0x65 Sets the timer register duty pulse 14 0625µs 16 2 fcgck 0x465 LD T00PWM 0x04 Sets the timer register duty pulse LD T001CR 0x06 Starts TC00 and TC01 Source clock Counter Timer start 1 0 km 0001 km km Duty pulse 256 counts Cycle 1 256 counts Cycle 2 256 counts Cycle 9 256 counts Cycle 16 Cycle 17 rs 0011 rs Write to T00PWM Double buffer Match detection Write m 0001 Write s 0011 Becomes the lev...

Page 213: ...DV9CK 0 SYSCR1 DV9CK 1 000 fcgck 211 fs 24 fs 24 204 8µs 488 2µs 52 4ms 838 9ms 125ms 2000ms 001 fcgck 210 fs 23 fs 23 102 4µs 244 1µs 26 2ms 419 4ms 62 5ms 1000ms 010 fcgck 28 fcgck 28 25 6µs 6 6ms 104 9ms 011 fcgck 26 fcgck 26 6 4µs 1 6ms 26 2ms 100 fcgck 24 fcgck 24 1 6µs 409 6µs 6 6ms 101 fcgck 22 fcgck 22 400ns 102 4µs 1 6ms 110 fcgck 2 fcgck 2 200ns 51 2µs 819 2µs 111 fcgck fcgck fs 22 100ns...

Page 214: ... written to T01PWM the set values of the four timer registers become effective at the same time Set the initial state of the PPG1 pin at T01MOD TFF1 Setting T01MOD TFF1 to 0 selects the L level as the initial state of the PPG1 pin Setting T01MOD TFF1 to 1 selects the H level as the initial state of the PPG1 pin If the PPG1 pin is set as the function output pin in the port setting while the timer i...

Page 215: ...g the timer operation the set values are immediately stored in T01 00PWM and T01 00REG Subsequently the match detection is executed using new set values If the value set to T01 00PWM or T01 00REG is smaller than the up counter value the PPG1 pin is not reversed until the up counter overflows and a match detection is executed using a new set value If the value set to T01 00PWM or T01 00REG is equal...

Page 216: ... TFF1 Write to T01PWM Write g Write k Write q INTT00 interrupt request INTT00 interrupt request 1 gh 1 km 1 gh 0 T01 00PWM T001CR T01RUN ab cd ef Write to T01REG Double buffer Write a Write c Write e Write to T00REG Write b Write d Write f ab Timer stop Match detection km km 1 km qr 1 qr 1 0 cd 1 0 cd 1 0 0 ef Match detection Counter clear Counter clear Counter clear Counter clear T01MOD TFF1 PPG1...

Page 217: ...lock 15 2 Control The real time clock is controlled by following resisters Low power consumption register 2 POFFCR2 7 6 5 4 3 2 1 0 0x0F76 Bit Symbol RTCEN SIO0EN Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 RTCEN RTC control 0 1 Disable Enable SIO0EN SIO0 control 0 1 Disable Enable Real time clock control register RTCCR 0x0FC8 7 6 5 4 3 2 1 0 Bit Symbol RTCSEL RTCRUN Rea...

Page 218: ...e clock unusable When using the real time clock for the first time be sure to set POFFCR2 RTCEN to 1 in the initial setting of the program before the real time clock control registers are operated Do not change POFFCR2 RTCEN to 0 during the real time clock operation Otherwise real time clock may operate unexpectedly 15 3 2 Enabling disabling the real time clock operation Setting RTCCR RTCRUN to 1 ...

Page 219: ...the real time clock starts counting of the low frequency clock When the interrupt generation interval selected at RTCCR RTCSEL is reached a real time clock interrupt request INTRTC is generated and the counter continues counting 15 4 2 Disabling the real time clock operation Clear RTCCR RTCRUN to 0 When RTCCR RTCRUN is cleared to 0 the binary counter for the real time clock is cleared to 0 and sto...

Page 220: ...15 Real Time Clock RTC 15 4 Real Time Clock Operation TMP89FM42 ...

Page 221: ... 1 and Table 16 2 Table 16 1 SFR Address Assignment UARTxCR1 address UARTxCR2 address UARTxDR address UARTxSR address RDxBUF address TDxBUF address UART0 UART0CR1 0x001A UART0CR2 0x001B UART0DR 0x001C UART0SR 0x001D RD0BUF 0x001E TD0BUF 0x001E UART1 UART1CR1 0x0F54 UART1CR2 0x0F55 UART1DR 0x0F56 UART1SR 0x0F57 RD1BUF 0x0F58 TD1BUF 0x0F58 Table 16 2 Pin Names Serial data input pin Serial data outpu...

Page 222: ...7 fcgck 28 PPGA0 output TCA0 output Baud rate generator Transmit RT clock Receive RT clock 2 4 2 2 2 Noise rejection circuit Shift register Shift register IrDA control S A B Y Counter Counter Transmit control circuit Receive control circuit Selector Frequency divider UART0CR1 UART0 control register 1 INTTXD0 interrupt request INTRXD0 interrupt request UART0 transmit data buffer UART0 receive data ...

Page 223: ...r UART0DR The operating status can be moni tored using the UART status register UART0SR Low power consumption register 1 POFFCR1 7 6 5 4 3 2 1 0 0x0F75 Bit Symbol SBI0EN UART1EN UART0EN Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 SBI0EN I2C0 control 0 1 Disable Enable UART1EN UART1 control 0 1 Disable Enable UART0EN UART0 control 0 1 Disable Enable ...

Page 224: ... prevent STOPBT EVEN PE IRDASEL and BRG from being changed accidentally during the UART communication the register cannot be rewritten during the UART operation For details refer to 16 4 Protection to Prevent UART0CR1 and UART0CR2 Registers from Being Changed Note 7 When the STOP IDLE0 or SLEEP0 mode is activated TXE and RXE are cleared to 0 and the UART stops Other bits keep their values UART0 co...

Page 225: ...0 output the value set to UART0DR has no meaning Note 3 When the STOP IDLE0 or SLEEP0 mode is activated the UART stops automatically but each bit value of UART0DR remains unchanged UART0 control register 2 UART0CR2 7 6 5 4 3 2 1 0 0x001B Bit Symbol RTSEL RXDNC STOPBR Read Write R R R W R W R W After reset 0 0 0 0 0 0 0 0 RTSEL Selects the number of RT clocks Odd numbered bits of transfer frame Eve...

Page 226: ...parity error Parity error FERR Framing error flag 0 1 No framing error Framing error OERR Overrun error flag 0 1 No overrrun error Overrun error RBSY Receive busy flag 0 1 Before receiving or end of receiving On receiving RBFL Receive buffer full flag 0 1 Receive buffer empty Receive buffer full TBSY Transmit busy flag 0 1 Before transmission or end of transmission On transmitting TBFL Transmit bu...

Page 227: ... ders the UART unusable Setting POFFCR1 UART0EN to 1 enables the basic clock supply to UART0 and ren ders the UART usable After reset POFFCR1 UART0EN is initialized to 0 and this renders the UART unusable When using the UART for the first time be sure to set POFFCR1 UART0EN to 1 in the initial setting of the program before the UART control register is operated Do not change POFFCR1 UART0EN to 0 du...

Page 228: ...d on the register when it is protected from being changed the bits remain unchanged and keep their previous values Table 16 3 Changing of UART0CR1 and UART0CR2 Bit to be changed Function Conditions that allow the bit to be changed UART0CR1 TXE UART0SR TBSY UART0CR1 RXE UART0SR RBSY UART0CR1 STOPBT Transmit stop bit length Both of these bits are 0 UART0CR1 EVEN Parity selection All of these bits ar...

Page 229: ...old the value Hold the value Hold the value Hold the value Hold the value Hold the value UART0SR PERR FERR OERR RBSY RBFL TBSY TBFL Cleared to 0 Cleared to 0 Cleared to 0 Cleared to 0 Cleared to 0 Cleared to 0 Cleared to 0 UART0DR UART0DR7 UART0DR6 UART0DR5 UART0DR4 UART0DR3 UART0DR2 UART0DR1 UART0DR0 Hold the value Hold the value Hold the value Hold the value Hold the value Hold the value Hold th...

Page 230: ...d odd numbered or no parity Stop bit selectable from 1 bit or 2 bits Figure 16 2 Transfer Data Format 16 7 Infrared Data Format Transfer Mode The TXD0 pin can output data in the infrared data format IrDA by the setting of the IrDA output control register Setting UART0CR1 IRDASEL to 1 allows the TXD0 pin to output data in the infrared data format Figure 16 3 Example of Infrared Data Format Comparis...

Page 231: ...00 0y000 0y000 0y000 Error 0 0 0 87 0 70 0 0 1 48 1 41 0 0 0 57600 UART0DR 0x0A 0x08 0x07 0x06 0x06 0x04 0x04 0x03 0x01 0x00 RTSEL 0y000 0y011 0y000 0y010 0y010 0y100 0y100 0y100 0y100 0y100 Error 1 36 0 44 0 1 59 0 79 2 12 0 39 2 12 2 12 2 12 38400 UART0DR 0x10 0x0C 0x0B 0x09 0x09 0x07 0x07 0x06 0x06 0x02 RTSEL 0y011 0y000 0y000 0y000 0y011 0y001 0y000 0y011 0y010 0y100 Error 1 17 0 16 0 0 0 81 1...

Page 232: ...selected at UART0CR1 BRG the number of times of UART0DR set value 1 Especially when UART0CR2 RTSEL is set to 0y001 or 0y011 two types of RT clocks alternate at each bit so that the pseudo baud rates of RT 15 5 clocks and RT 16 5 clocks can be generated The number of RT clocks per bit of transfer frame is shown in Figure 16 4 For example when fcgck is 4 MHz UART0CR2 RTSEL is set to 0y000 and UART0D...

Page 233: ...the communication may fail due to factors such as frequency errors of external controllers for example a personal computer and oscillators and the load capacity of the communication pin Figure 16 5 UART0DR Calculation Method When BRG Is Set to fcgck Start 1 2 3 4 5 6 7 8 9 10 11 12 Bit 0 Stop 1 Start Bit 0 Stop 1 Stop 2 Stop 1 Stop 1 Stop 2 Start Bit 0 Bit 0 Start Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit...

Page 234: ...00 Hz 1 6 35714 baud 6 99 40404 baud 5 22 38095 baud 0 79 36866 baud 3 99 39216 baud 2 12 1 6 1 6 1 5 1 5 UARTDR 16 38400 baud UARTDR calculation Generated baud rate RTSEL 4000000 Hz 16 6 1 4000000 Hz 16 5 5 1 4000000 Hz 15 6 1 4000000 Hz 15 5 6 1 4000000 Hz 17 5 1 001 UARTDR 16 5 38400 baud 010 UARTDR 15 38400 baud 011 UARTDR 15 5 38400 baud 100 UARTDR 17 38400 baud ...

Page 235: ...s is changed Figure 16 7 Figure 16 7 Data Sampling in Each Case of UARTCR2 RTSEL RT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 Bit 0 Start Bit Bit 0 Start Bit b UARTCR2 RTSEL is 001B RT clock Internal received data RT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 Bit 0 Start Bit Bit 0 Start Bit a UARTCR2 RTSEL is 000B RT clock RXD0 pin RXD0 pin RXD0 pin RXD...

Page 236: ...ts and the data receiving restarts with the start bit Figure 16 8 Start Bit Sampling RT15 14 13 12 11 10 9 8 7 6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 Bit 0 Start Bit Start Bit Bit 0 RT clock RXD0 pin Shift register Noise Bit 0 Internal received data Error because the start bit is 1 Counting is suspended until the next falling edge is detected Receiving continues be...

Page 237: ...e rejection 01 UART0DR 1 Transfer base clock frequency 2 UART0DR 1 Transfer base clock frequency 10 2 UART0DR 1 Transfer base clock frequency 4 UART0DR 1 Transfer base clock frequency 11 4 UART0DR 1 Transfer base clock frequency 8 UART0DR 1 Transfer base clock frequency Receiving continues because the start bit is 0 The received data is taken into the shift register 15 14 13 12 11 10 9 8 7 6 5 4 3...

Page 238: ...nd is transferred to the shift register Note 2 Under the conditions shown in Table 16 9 the TXD0 pin output is fixed at the L or H level according to the setting of UART0CR1 IRDASEL 16 11 2Data receive operation Set UART0CR1 RXE to 1 When data is received via the RXD0 pin the received data is transferred to RD0BUF receive data buffer At this time the transmitted data includes a start bit stop bit ...

Page 239: ...when RD0BUF is read subsequently In this case UART0SR PERR will be cleared to 0 when UART0SR is read again and RD0BUF is read Figure 16 10 Occurrence of Parity Error RXD0 pin input Indeterminate Data reading PERR is cleared to 0 when RD0BUF is read after reading PERR 1 INTRXD0 interrupt request UART0SR PERR Start Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Parity Stop Reading of UART0SR Reading of RD0...

Page 240: ...eived in the sampling of the stop bit FERR is cleared to 0 when RD0BUF is read after reading FERR 1 FERR is cleared to 0 when RD0BUF is read after reading FERR 1 Sampling INTRXD0 interrupt request UART0SR FERR When the external baud rate is slower than the internally set baud rate When the external baud rate is faster than the internally set baud rate Start Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 ...

Page 241: ...occurred in the previous received data the data stored in RD0BUF Figure 16 13 If UART0SR OERR is 1 when UART0SR is read UART0SR OERR will be cleared to 0 when RD0BUF is read subsequently Figure 16 14 If UART0SR OERR is set to 1 after UART0SR is read UART0SR OERR will not be cleared to 0 when RD0BUF is read subsequently In this case UART0SR OERR will be cleared to 0 when UART0SR is read again and R...

Page 242: ...Bit0 Parity Stop Data C Data D The contents of data B are discarded and those of data A are maintained The contents of data C are discarded and those of data A are maintained The contents of data D are discarded and those of data A are maintained The parity is OK The parity is OK The flag is not set even if a framing error occurs RXD0 pin input Data A Data A An interrupt request is generated An in...

Page 243: ...RT0SR OERR UART0SR RBFL Start Bit0 Bit1 Bit7 Stop Start Bit0 Bit1 Bit7 Stop Reading of UART0SR Reading of RD0BUF RD0BUF RXD0 pin input Data A Data A Reading of data A The contents of data B are discarded and those of data A are maintained Data B OERR is cleared to 0 when RD0BUF is read after reading OERR 1 RBFL is cleared to 0 when RD0BUF is read after reading RBFL 1 INTRXD0 interrupt request UART...

Page 244: ...T0SR is read UART0SR RBFL will not be cleared to 0 when RD0BUF is read subsequently In this case UART0SR RBFL will be cleared to 0 when UART0SR is read again and RD0BUF is read Figure 16 15 Occurrence of Receive Data Buffer Full RXD0 pin input Data A Data A Reading of data A Data B Reading of data B Data B RBFL is cleared to 0 when RD0BUF is read after reading RBFL 1 INTRXD0 interrupt request UART...

Page 245: ...er and trans mission is started UART0SR TBFL is cleared to 0 At this time an INTTXD0 interrupt request is gener ated Writing data into TD0BUF sets UART0SR TBFL to 1 Figure 16 17 Occurrence of Transmit Buffer Full TXD0 pin input INTTXD0 interrupt request UART0SR TBFL Start Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Stop Start Bit0 Bit1 Bit6 Bit7 Stop Writing of TD0BUF UART0SR TBSY UART0CR1 TXE Data A ...

Page 246: ... transfer Basically an overrun error occurs when the internal software process ing cannot follow the data transfer speed It is recommended to slow the transfer baud rate or modify the software to execute flow control Figure 16 18 Example of Receiving Process Note 1 If multiple interrupts are used in the INTRXD0 interrupt subroutine the interrupt should be enabled after reading UART0SR and RD0BUF R...

Page 247: ... been completed properly 1 0 1 Receiving has been completed properly but some pieces of data could not be received 1 1 0 Received data has erroneous value s 1 1 1 Received data has erroneous value s and some pieces of data could not be received Table 16 11 Flag Judgments When a Receive Interrupt Is Used FERR PERR OERR State 0 0 Receiving has been completed properly 0 1 Receiving has been completed...

Page 248: ...rties VSS 0 V Topr 40 to 85 C Item Condition Min Typ Max Unit TXD output pulse time RT clock 3 16 Transfer baud rate 2400 bps 78 13 µs Transfer baud rate 9600 bps 19 53 Transfer baud rate 19200 bps 9 77 Transfer baud rate 38400 bps 4 88 Transfer baud rate 57600 bps 3 26 Transfer baud rate 115200 bps 1 63 ...

Page 249: ...Changed example from fcgck 8MHz to fcgck 4MHz 16 8 1 2 Calculation of set values of UART0CR2 RTSEL and UART0DR Changed example from fcgck 6MHz to fcgck 4MHz Figure 16 6 Example of UART0DR Calculation Changed example from fcgck 6MHz to fcgck 4MHz Figure 16 1 Asynchronous Serial Interface UART Added PPGA0 output to TCA0 output ...

Page 250: ...16 Asynchronous Serial Interface UART 16 15 Revision History TMP89FM42 ...

Page 251: ... of the clock synchronization type Table 17 1 SFR Address Assignment SIOxCR address SIOxSR address SIOxBUF address Serial interface 0 SIO0CR 0x001F SIO0SR 0x0020 SIO0BUF 0x0021 Table 17 2 Pin Names Serial clock input output pin Serial data input pin Serial data output pin Serial interface 0 SCLK0 pin SI0 pin SO0 pin ...

Page 252: ...s The I O port register settings are required to use these pins for a serial interface For details refer to the chapter of I O ports Shift register on transmitter Shift register on receiver Control circuit Shift clock Internal clock Port Note Port Note MSB LSB selection Port Note Internal bus Internal bus SIO0CR SIO0SR SIO0BUF SIO0BUF INTSIO0 interrupt request SO0 pin SI0 pin SCLK0 pin ...

Page 253: ...O0BUF has never received data it is read as 0 When data is written into it the data is treated as the transmit data Low power consumption register 2 POFFCR2 7 6 5 4 3 2 1 0 0x0F76 Bit Symbol RTCEN SIO0EN Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 RTCEN RTC control 0 1 Disable Enable SIO0EN SIO0 control 0 1 Disable Enable Serial interface buffer register SIO0BUF 7 6 5 4 ...

Page 254: ...ed Note 6 When STOP IDLE0 or SLEEP0 mode is activated SIOM is automatically cleared to 00 and SIO stops the operation At the same time SIOS is cleared to 0 However the values set for SIOEDG SIOCKS and SIODIR are maintained Serial interface control register SIO0CR 7 6 5 4 3 2 1 0 0x001F Bit Symbol SIOEDG SIOCKS SIODIR SIOS SIOM Read Write R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 SIOEDG Trans...

Page 255: ...r reset 0 0 0 0 0 0 0 0 SIOF Serial transfer operation status monitor 0 1 Transfer not in progress Transfer in progress SEF Shift operation status monitor 0 1 Shift operation not in progress Shift operation in progress OERR Receive overrun error flag 0 1 No overrun error has occurred At least one overrun error has occurred REND Receive completion flag 0 1 No data has been received since the last r...

Page 256: ...ers the serial interface unusable Setting POFFCR2 SIO0EN to 1 enables the basic clock supply to serial interface 0 and allows the serial interface to operate After reset POFFCR2 SIO0EN are initialized to 0 and this renders the serial interface unusable When using the serial interface for the first time be sure to set POFFCR2 SIO0EN to 1 in the initial setting of the program before the serial inter...

Page 257: ...th the external and internal clocks For details refer to 17 4 3 Transfer edge selection 17 4 3 Transfer edge selection The serial data transfer edge can be selected by using SIOCR SIOEDG When SIOCR SIOEDG is 0 the data is transmitted in synchronization with the falling edge of the clock and the data is received in synchronization with the rising edge of the clock When SIOCR SIOEDG is 1 the data is...

Page 258: ...first bit of the next transfer R1 R0 R2 R3 R4 R5 R6 R7 T1 T0 T2 T3 T4 T5 T6 T7 SLCK0 pin SO0 pin SI0 pin When SIOCR SIOEDG 0 R1 R0 R2 R3 R4 R5 R6 R7 T1 T0 T2 T3 T4 T5 T6 T7 SCLK0 pin SO0 pin SI0 pin When SIOCR SIOEDG 1 C7 C6 D0 D1 D2 A7 A6 B0 B1 B2 tBI Leading edge at the 1st bit transmit edge Trailing edge at the 8th bit receive edge SCLK0 pin SO0 pin SI0 pin Symbol Name Minimum time tBI Interval...

Page 259: ... SIO0BUF to the shift register and then transmitted as the serial data from the SO0 pin according to the settings of SIO0CR SIOEDG SIOCKS and SIODIR The serial data becomes undefined if the transmit operation is started without writing any transmit data to SIO0BUF In the internal clock operation the serial clock of the selected baud rate is output from the SCLK0 pin In the external clock operation...

Page 260: ...ading SIO0SR 3 When an internal or external clock is used and SIO0SR TBFL is 1 When the data transmission is completed SIO0SR TBFL is cleared to 0 The data in SIO0BUF is transferred to the shift register and the transmission of subsequent data is started At this time SIO0SR SEF is set to 1 and an INTSIO0 interrupt request is generated 17 5 1 5 Stopping the transmit operation Set SIO0CR SIOS to 0 t...

Page 261: ...ted after transmission in case of reserved stop The level is held for the period of the internal clock 1 2 Automatic wait 01 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Data C SO0 pin output Internal clock SCLK0 pin output INTSIO0 interrupt request Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Write to SIO0BUF SIO0BUF A B C D SIO0CR SIOS SIO0CR SIOM SIO0SR SIOF SIO0SR SEF SIO0SR TBFL Data A D...

Page 262: ... in the operation with an external clock Returned to the H level by setting SIOCR1 SIOM to 00 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Data C SIO0CR SIOM 01 00 SO0 pin output SCLK0 pin input INTSIO0 interrupt request Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Write to SIO0BUF SIO0BUF A B C D SIO0CR SIOS SIO0SR SIOF SIO0SR SEF SIO0SR TBFL Data A Data C Writing data A Writing data B Writi...

Page 263: ... SIO0CR SIOS SIO0SR SIOF SIO0SR SEF SIO0SR TBFL SIO0SR UERR Data A Data A Data B Writing data A Writing data B Reading SIO0SR Writing data C Reserved stop Start operation Stopped while keeping the current level in the operation with an external clock Returned to the H level by setting SIOCR1 SIOM to 00 Transferred to the buffer immediately after writing Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Data...

Page 264: ...ation on completion of reception When the data reception is completed the data is transferred from the shift register to SIO0BUF and an INTSIO0 interrupt request is generated The receive completion flag SIO0SR REND is set to 1 In the operation with the internal clock the serial clock output is stopped until the receive data is read from SIO0BUF automatic wait At this time SIO0SR SEF is set to 0 By...

Page 265: ...stops the operation regardless of the SIO0SR SEF value If the internal clock is selected the SCLK0 pin returns to the initial level Figure 17 8 8 bit Receive Mode Internal Clock and Reserved Stop SI0 pin input Internal clock SCLK0 pin output INTSIO0 interrupt request Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Read SIO0BUF SIO0BUF A C SIO0CR SIOS SIO0SR SIOF SIO0SR SEF SIO0SR REND Data A Reading data ...

Page 266: ...SR REND Data A Reading data A Returned to the initial level Reserved stop Forced stop Forced stop Start operation Start operation Automatic wait 10 00 00 10 Bit0 Bit1 Bit2 Bit3 Bit0 Bit1 Bit2 Data B Data C Returned to the initial level SI0 pin input SCLK0 pin input INTSIO0 interrupt request Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Read SIO0BUF SIO0BUF A B C SIO0CR SIOS SIO0SR SIOF SIO0SR SEF SIO0SR...

Page 267: ...IO0SR REND Data A Reading data A Reading data C Forced stop Start operation Start operation 10 00 10 Data B Data B is discarded Data C SI0 pin input SCLK0 pin input INTSIO0 interrupt request Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Read SIO0BUF SIO0BUF A Read SIO0SR SIO0CR SIOS SIO0CR SIOM SIO0SR SIOF SIO0SR SEF SIO0SR ...

Page 268: ...a is transmit ted from the SO0 pin according to the settings of SIO0CR SIOEDG SIOCKS and SIODIR At the same time the serial data is received from the SI0 pin according to the settings of SIO0CR SIOEDG SIOCKS and SIODIR In the internal clock operation the serial clock of the selected baud rate is output from the SCLK0 pin In the external clock operation an external clock must be supplied to the SCL...

Page 269: ...to 1 17 5 3 5 Stopping the transmit receive operation Set SIO0CR SIOS to 0 to stop the transmit receive operation When SIO0SR SEF is 0 or when the shift operation is not in progress the operation is stopped immediately Unlike the transmit mode no INTSIO0 interrupt request is generated in this state When SIO0SR SEF is 1 the operation is stopped after the 8 bit data is received completely At this ti...

Page 270: ...te to SIO0BUF SIO0BUF Write buffer D E F G SIO0BUF Read buffer A B C SIO0CR SIOS SIO0SR SIOF SIO0SR SEF SIO0SR TBFL SIO0SR REND Data A Data B Writing data D Read SIO0BUF Reading data A Reading data B Reading data C Writing data E Writing data F Writing data G Reserved stop Start operation Wait Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Data C SO0 pin output Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit...

Page 271: ...SIO0BUF Read buffer A B C SIO0CR SIOS SIO0CR SIOM SIO0SR SIOF SIO0SR SEF SIO0SR TBFL SIO0SR REND Data A 11 00 Data B Writing data D Read SIO0BUF Reading data A Reading data B Reading data C Writing data E Writing data F Writing data G Reserved stop Start operation Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Data C SO0 pin output Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit...

Page 272: ...t5 Bit6 Bit7 Write to SIO0BUF SIO0BUF Write buffer D F G SIO0BUF Read buffer A C Read SIO0SR SIO0CR SIOS SIO0SR SIOF SIO0SR SEF SIO0SR TBFL SIO0SR REND SIO0SR OERR SIO0SR UERR Data A Data B Writing data D Read SIO0BUF Reading data A Reading data C Writing data F Writing data G Reserved stop Start operation Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Data C SO0 pin output Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 ...

Page 273: ...e tSOD 50 50 SCLK cycle time tSCY External clock operation SO pin and SCLK pin load capacity 100 pF 2 fcgck SCLK L pulse width tSCYL 1 fcgck SCLK H pulse width tSCYH 1 fcgck SI input setup time tSIS 50 SI input hold time tSIH 50 SO output delay time tSOD 0 60 SCLK low level input voltage tSCLKL 0 VDD 0 30 V SCLK high level input voltage tSCLKH VDD 0 70 VDD SCLK pin tSIS VSCLKL VSCLKH tSCYL tSCYH t...

Page 274: ... Interface SIO 17 7 Revision History TMP89FM42 17 7 Revision History Rev Description RA001 Table 17 3 Transfer Baud Rate Revised table Add some fcgck condition 17 6 AC Characteristics Revised table Add some fcgck condition ...

Page 275: ...gure 18 1 Device Connections Communications are implemented between a master and slave The master transmits the start condition the slave addresses the direction bit and the stop condition to the slave s connected to the bus and transmits and receives data The slave detects these conditions transmitted from the master by the hardware and transmits and receives data The data format of the I2 C bus ...

Page 276: ... to 8 bits 1 1 S A C K A C K A C K P Slave address Data Data 1 to 8 bits 1 R W 8 bits 1 1 1 or more 1 or more 1 to 8 bits 1 1 1 S A C K A C K A C K P Slave address Data Data Slave address 1 to 8 bits 1 R W 8 bits A C K R W S a Addressing format b Addressing format with restart S R W ACK P Start condition Direction bit Acknowledge bit Stop condition 8 bits 1 1 or more 1 to 8 bits 1 1 S A C K A C K ...

Page 277: ...lock control circuit Software reset circuit Transfer control circuit Shift register Data control circuit l o r t n o c t u p t u o t u p n I SDA SCL Noise canceller Noise canceller C B T S R W S N I P B B X R T T S M K C A K C A O N K C S S L A B R L 0 S A S A A L A X R T T S M B B A S INTSBI Interrupt request ...

Page 278: ...When SBI0EN is cleared to 0 the clock supply to the serial bus interface is stopped At this time the data written to the serial bus interface control registers is invalid When the serial bus interface is used set SBI0EN to 1 and then write the data to the serial bus interface control registers Low power consumption register 1 POFFCR1 7 6 5 4 3 2 1 0 0x0F75 Bit Symbol SBI0EN UART1EN UART0EN Read Wr...

Page 279: ...n acknowledge signal ACK Master mode Slave mode 0 Not generating the clocks for an acknowledge signal Generate an interrupt request when the data transfer is finished non acknowledgement mode Generate an interrupt request when the data transfer is finished non acknowledgement mode 1 Generate the clocks for an acknowledge signal and an inter rupt request when the data trans fer is finished acknowle...

Page 280: ...ll the bits of the SBI0CR2 register except SBI0CR2 SBIM and the SBI0CR1 I2C0AR and SBI0SR2 registers are initialized Note 4 When the operation is switched to STOP IDLE0 or SLOW mode the SBI0CR2 register except SBI0CR2 SBIM and the SBI0CR1 I2C0AR and SBI0DBR registers are initialized MST Master slave selection 0 Slave 1 Master TRX Transmitter receiver selection 0 Receiver 1 Transmitter BB Start sto...

Page 281: ...il it is released Note 4 To set SBI0CR2 PIN to 1 by writing the dummy data to SBI0DBR write 0x00 Writing any data other than 0x00 causes an improper value in the subsequently received data Note 5 When the operation is switched to STOP IDLE0 or SLOW mode the SBI0CR2 register except SBI0CR2 SBIM and the SBI0CR1 I2C0AR and SBI0DBR registers are initialized 18 4 Functions 18 4 1 Low Power Consumption ...

Page 282: ...ly The acknowledgment mode is activated by setting SBI0CR1 ACK to 1 The master device generates the clocks for an acknowledge signal and outputs an acknowledge signal in the receiver mode The slave device counts the clocks for an acknowledge signal and outputs an acknowledge sig nal in the receiver mode The non acknowledgment mode is activated by setting SBI0CR1 ACK to 0 The master device does not...

Page 283: ...ceive an acknowledge signal from the receiver during the period of the clocks for an acknowledge signal In the receiver mode the SDA0 pin is pulled down to the low level and an acknowledge signal is generated during the period of the clocks for an acknowledge signal In the slave mode When a match between the received slave address and the slave address set to I2C0AR SA is detected or when a GENERA...

Page 284: ...LOW periods of the serial clock to be output in the master mode Table 18 2 States of the SCL0 and SDA0 Pins in the Acknowledgment Mode Mode Pin Condition Transmitter Receiver Master SCL0 Add the clocks for an acknowledge signal Add the clocks for an acknowl edge signal SDA0 Release the pin to receive an acknowledge signal Output the low level as an acknowledge signal to the pin Slave SCL0 Count th...

Page 285: ...lly input clock regardless of the SBI0CR1 SCK set ting Figure 18 7 SCL Input 18 4 4 2 Clock synchronization In the I2 C bus due to the structure of the pin in order to drive a bus with a wired AND a master device which pulls down a clock pulse to low will in the first place invalidate the clock pulse of another master device which generates a high level clock pulse Therefore the master outputting ...

Page 286: ...o set a master device SBI0CR2 MST should be set to 1 To set a slave device SBI0CR2 MST should be cleared to 0 When a stop condition on the bus or an arbitration lost is detected SBI0CR2 MST is cleared to 0 by the hardware 18 4 6 Transmitter receiver selection To set the device as a transmitter SBI0CR2 TRX should be set to 1 To set the device as a receiver SBI0CR2 TRX should be cleared to 0 For the...

Page 287: ...ting 1 to SBI0CR2 MST SBI0CR2 TRX and SBI0CR2 PIN and writing 0 to SBI0CR2 BB When a stop condition is generated The SCL line on a bus is pulled down to the low level by another device a stop condition is generated after releasing the SCL line Figure 18 10 Stop Condition Generation The bus condition can be indicated by reading the contents of SBI0SR2 BB SBI0SR2 BB is set to 1 when the start condit...

Page 288: ...SBI0CR2 PIN being set to 1 until the SBI0 pin is released takes tLOW Although SBI0CR2 PIN can be set to 1 by the software SBI0CR2 PIN can not be cleared to 0 by the software 18 4 9 Setting of serial bus interface mode SBI0CR2 SBIM is used to set serial bus interface mode Setting SBI0CR2 SBIM to 1 selects the serial bus interface mode Setting it to 0 selects the port mode Set SBI0CR2 SBIM to 1 in o...

Page 289: ... is data in Master 2 Data transmitted from Master 1 becomes invalid The state in Master 1 is called arbitration lost A master device which loses arbitration releases the SDA pin and the SCL pin in order not to effect data transmitted from other masters with arbitration When more than one master sends the same data at the first word arbitration occurs continuously after the second word Figure 18 12...

Page 290: ...d When a serial bus interface circuit operates in the free data format I2C0AR ALS 1 SBI0SR2 AAS is set to 1 after receiving the first 1 word of data SBI0SR2 AAS is cleared to 0 by writing data to the SBI0DBR or reading data from the SBI0DBR Figure 18 14 Changes in the Slave Address Match Detection Monitor SCL pin SDA pin SCL pin SDA pin D4A 1 2 3 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 Master A Master...

Page 291: ...enerated an acknowledge signal is read by reading the contents of SBI0SR2 LRB Figure 18 16 Changes in the Last Received Bit Monitor 18 4 15Slave address and address recognition mode specification When the serial bus interface circuit is used in the I2 C bus mode clear I2C0AR ALS to 0 and set I2C0AR SA to the slave address When the serial bus interface circuit is used with a free data format not to...

Page 292: ...and the direction bit which are set to the SBI0DBR are output The time from generating the START condition until the falling SBI0 pin takes tHIGH An interrupt request occurs at the 9th falling edge of a SCL clock cycle and SBI0CR2 PIN is cleared to 0 The SCL0 pin is pulled down to the low level while SBI0CR2 PIN is 0 When an interrupt request occurs SBI0CR2 TRX changes by the hardware according to...

Page 293: ...nsmitted data to SBI0DBR After writing the data SBI0CR2 PIN becomes 1 a serial clock pulse is generated for transfer ring the subsequent 1 word data from the SCL0 pin and then the 1 word data is transmitted from the SDA0 pin After the data is transmitted an interrupt request occurs SBI0CR2 PIN become 0 and the SCL0 pin is set to the low level If the data to be transferred is more than one word in ...

Page 294: ...ts a clock pulse for 1 word data transfer and the acknowledge signal by writing data to the SBI0DBR or setting SBI0CR2 PIN to 1 after reading the received data Figure 18 19 Example when SBI0CR1 BC 000 and SBI0CR1 ACK 1 To make the transmitter terminate transmission execute following procedure before receiving a last data 1 Read the received data 2 Clear SBI0CR1 ACK to 0 and set SBI0CR1 BC to 000 3...

Page 295: ...ating the serial bus interface interrupt request INTSBI0 are follows At the end of the acknowledge signal when the received slave address matches the value set by the I2C0AR SA with SBI0CR1 NOACK set at 0 At the end of the acknowledge signal when a GENERAL CALL is received with SBI0CR1 NOACK set at 0 At the end of transferring or receiving after matching of slave address or receiving of GENERAL CA...

Page 296: ...s interface circuit receives a slave address of which the value of the direc tion bit sent from the master is 1 0 0 In the slave transmitter mode the serial bus interface circuit finishes the trans mission of 1 word data Check SBI0SR2 LRB If it is set to 1 set SBI0CR2 PIN to 1 since the receiver does not request subsequent data Then clear SBI0CR2 TRX to 0 to release the bus If SBI0SR2 LRB is set t...

Page 297: ...een a master device and a slave device during transferring data The following explains how to restart the serial bus interface circuit Clear SBI0CR2 MST SBI0CR2 TRX and SBI0CR2 BB to 0 and set SBI0CR2 PIN to 1 The SDA0 pin retains the high level and the SCL0 pin is released Since this is not a stop condition the bus is assumed to be in a busy state from other devices Check SBI0SR2 BB until it beco...

Page 298: ...ave device before the STOP condition is generated To stop the transmission the master device make the slave device receiving a negative acknowledge Therefore SBI0SR2 LRB is 1 before generating the Restart and it can not be confirmed that SCL line is not pulled down by other devices Please confirm the SCL line state by read ing the port Figure 18 22 Timing Diagram When Restarting Example Generate a...

Page 299: ...LOW n fcgck n fcgck µs High level period of SCL clock output tHIGH m fcgck m fcgck µs Low level period of SCL clock input tLOW 5 fcgck 5 fcgck µs High level period of SCL clock input tHIGH 3 fcgck 3 fcgck µs Restart condition setup time tSU STA Depends on the software Depends on the software µs Data hold time tHD DAT 0 5 fcgck 0 5 fcgck µs Data setup time tSU DAT 250 100 ns Rising time of SDA and ...

Page 300: ...18 Serial Bus Interface SBI 18 6 AC Specifications TMP89FM42 Figure 18 24 Definition of Timing No 2 SCL SBICR2 PIN SU SCL t ...

Page 301: ... Serial bus interface control register 1 Revised SCK description Added Note5 18 6 AC Specifications Revised fcgck description Table 18 6 AC Specifications Circuit Output Timing Revised value of SCL clock frequency Revised from normal mode to standard mode ...

Page 302: ...18 Serial Bus Interface SBI 18 7 Revision History TMP89FM42 ...

Page 303: ...I7 through KWI0 19 1 Configuration Figure 19 1 Key on Wakeup Circuit Stop mode release signal to be released if set to 1 SYSCR1 RELM Selector Port Port Port Port Port Rising edge detection 0 1 S Y 7 6 5 4 3 2 1 0 KWUCR0 0x0FC4 Port Port Port Port 7 6 5 4 3 2 1 0 KWUCR1 0x0FC5 KWI0 KWI1 KWI2 KWI3 KWI4 KWI5 KWI6 KWI7 STOP ...

Page 304: ...ease level of KWI1 0 1 Low level High level KW1EN Input enable disable control of KWI1 pin 0 1 Disable Enable KW0LE STOP mode release level of KWI0 pin 0 1 Low level High level KW0EN Input enable disable control of KWI0 pin 0 1 Disable Enable Key on wakeup control register 1 KWUCR1 7 6 5 4 3 2 1 0 0x0FC5 Bit Symbol KW7LE KW7EN KW6LE KW6EN KW5LE KW5EN KW4LE KW4EN Read Write R W R W R W R W R W R W ...

Page 305: ...1 Starting STOP mode To start the STOP mode set SYSCR1 RELM to 1 level release mode and SYSCR1 STOP to 1 To use the key on wakeup function do not set SYSCR1 RELM to 0 edge release mode If the key on wakeup function is used in edge release mode STOP mode cannot be released although a rising edge is input into the STOP pin This is because the KWIm pin enabling inputs to be received is at a release l...

Page 306: ...t to a high level and the release level of KWI0 set to a low level connected to an internal pull up resistor of the KWI0 pin DI IMF 0 SET P4PU 0 KWI0 P40 connected to a pull up resistor LD KWUCR0 00000001B the KWI0 pin is set to enable inputs and its release level is set to a low level LD SYSCR1 10100000B Starting in level release mode ...

Page 307: ...ng the AD converter set an appropriate value to the I O port register which is also used as an analog input port For details see the section on I O ports Note 2 The DA converter current IREF is automatically cut off at times other than during AD conversion 4 10 AINDS R 2 R 2 R SAIN n Sample hold circuit A S EN DA converter Input selector Y Reference voltage 2 10 8 8 S R D A ACK AMD AD converted va...

Page 308: ...nalog channel in which to perform AD conversion selects an AD conversion operation mode and controls the start of the AD converter 2 AD converter control register 2 ADCCR2 This register selects the AD conversion time and monitors the operating status of the AD converter 3 AD converted value registers ADCDRH and ADCDRL These registers store the digital values generated by the AD converter ...

Page 309: ...LOW mode is started ADRS AMD and AINEN are initialized to 0 If you use the AD converter after returning to NORMAL mode you must reconfigure ADRS AMD and AINEN Note 5 After the start of AD conversion ADRS is automatically cleared to 0 0 is read AD converter control register 1 ADCCR1 7 6 5 4 3 2 1 0 0x0034 Bit Symbol ADRS AMD AINEN SAIN Read Write R W R W R W R W After reset 0 0 0 0 0 0 0 0 ADRS AD ...

Page 310: ...24 fcgck 1248 fcgck Reserved Reserved Table 20 1 ACK Settings and Conversion Times Relative to Frequencies Frequency fcgck ACK setting Conversion time 10MHz 8MHz 4MHz 2MHz 5MHz 2 5MHz 1MHz 0 5MHz 0 25 MHz 000 39 fcgck 19 5 µs 15 6 µs 39 0 µs 78 0 µs 156 0 µs 001 78 fcgck 19 5 µs 39 0 µs 15 6 µs 31 2 µs 78 0 µs 156 0 µs 010 156 fcgck 15 6 µs 19 5 µs 39 0 µs 78 0 µs 31 2 µs 62 4 µs 156 0 µs 011 312 ...

Page 311: ...are initialized to 0 Note 5 If an instruction to read ADCDRH is executed 0 is read from bits 7 through 2 Note 6 If AD conversion is finished in repeat mode in the interim between a read of ADCDRL and a read of ADCDRH the previ ous converted value is retained without overwriting the AD converted value register In this case the INTADC interrupt request is canceled and the conversion result is lost A...

Page 312: ...gister when AD conversion is being executed ADCCR2 ADBF 1 If the following operations are performed there is the possibility that AD conversion may not be executed properly Changing the ADCCR1 SAIN setting Setting ADCCR1 AINEN to 0 Changing the ADCCR1 AMD setting except a forced stop by setting AMD to 00 Setting ADCCR1 ADRS to 1 Figure 20 2 Single Mode 20 3 2 Repeat mode In repeat mode the voltage...

Page 313: ...tion If you want to force the AD converter to stop when AD conversion is ongoing in single mode or if you want to stop the AD converter when AD conversion is ongoing in repeat mode set ADCCR1 AMD to 00 If ADCCR1 AMD is set to 00 registers ADCCR2 EOCF ADCCR2 ADBF ADCDRL and ADCDRH are initialized to 0 Status of ADCDRL and ADCDRH A read of the conversion result will clear EOCF The INTADC interrupt r...

Page 314: ...erformed once again before reading the AD con verted value register ADCDRH In this case the previous conversion result is retained until AD conver sion is finished 20 5 Starting STOP IDLE0 SLOW Modes If STOP IDLE0 SLOW mode is started registers ADCCR1 ADRS AMD AINEN ADCCR2 EOCF ADBF ADCDRL and ADCDRH are initialized to 0 If any of these modes is started during AD conversion AD conver sion is suspe...

Page 315: ... correspond to AD converted 10 bit digital values as shown in Figure 20 4 Figure 20 4 Relationships between Analog Input Voltages and AD converted Values typical values 1 0 01H 02H 03H 3FDH 3FEH 3FFH 2 3 1021 1022 1023 1024 Analog input voltage 1024 AD converted value VAREF AVDD VSS ...

Page 316: ...possibility that the accuracy of AD conversion may deteriorate This also applies to pins other than analog input pins if one pin receives inputs or generates outputs noise may occur and its adjacent pins may be affected by that noise 20 7 3 Noise countermeasure The internal equivalent circuit of the analog input pins is shown in Figure 20 5 The higher the output imped ance of the analog input sour...

Page 317: ...les the flash memory to be controlled by the small number of pins The TMP89FM42 used in serial PROM mode supports on board programming which enables users to pro gram flash memory after the microcontroller is mounted on a user board Parallel PROM mode The parallel PROM mode allows the flash memory to be accessed as a stand alone flash memory by the program writer provided by a third party High spe...

Page 318: ... Show BOOTROM FAREA Flash memory area select control 00 Assign the data area 0x8000 through 0xFFFF to the data area 0x8000 through 0xFFFF standard mapping 01 Reserved 10 Assign the code area 0x8000 through 0xFFFF to the data area 0x8000 through 0xFFFF 11 Reserved Note 1 It is prohibited to make a setting in Reserved Note 2 The flash memory control register 1 has a double buffer structure comprised...

Page 319: ...AM Flash memory control register 1 monitor FLSCRM 7 6 5 4 3 2 1 0 0x0FD1 Bit Symbol FLSMDM BAREAM FAREAM ROMSELM Read Write R R R R R R After reset 0 0 0 0 0 0 0 0 FLSMDM Monitoring of FLSCR1 FLSMD status 0 1 FLSCR1 FLSMD 101 setting disabled FLSCR1 FLSMD 101 setting enabled BAREAM Monitoring of FLSCR1 BAREA status Value of currently enabled FLSCR1 BAREA FAREAM Monitoring of FLSCR1 FAREA status Va...

Page 320: ... All I O ports are controlled by PIN0 except the ports RXD0 TXD0 and SCLK0 which are used in serial PROM mode By using PIN1 the SCLK0 pin can be configured separately from other pins Flash memory standby control register FLSSTB 7 6 5 4 3 2 1 0 0x0FD2 Bit Symbol FSTB Read Write R R R R R R R W After reset 0 0 0 0 0 0 0 0 FSTB Flash memory standby control 0 1 Disable flash memory standby Enable flas...

Page 321: ...r the toggle operation is exe cuted with the execution of the command sequence and the toggle operation set to disable the executed com mand sequence or toggle operation takes no effect After a reset FLSCR1 FLSMD is initialized to 0y010 to disable the execution of the command sequence FLSCR1 FLSMD should normally be set to 0y010 except when a write or erase is to be per formed on the flash memory ...

Page 322: ...data area Additionally access to areas to which memory is not assigned should be avoided by executing an instruction or specifying such an area by using jump or call instructions Figure 21 1 Area Switching Using the FLSCR1 FAREA Setting 0x8000 through 0xFFFF AREA D1 in the data area and 0x8000 through 0xFFFF AREA C1 in the code area are mirror areas these two areas refer to the same physical addre...

Page 323: ... of 4KB BOOTROM is mapped If you do not want to map BOOTROM set 0xD5 on FLSCR2 CR1EN after setting FLSCR1 BAREA to 0 A set of codes for programming flash memory in serial PROM mode are built into BOOTROM and a sup port program API for performing an erase or write on flash memory in a simple manner is also built into one part in the BOOTROM area Therefore by calling a subroutine in the support prog...

Page 324: ...ured value will be invalidated and does not take effect Data area If SYSSR4 RAREAS 0 FLSCR1 BAREA 0 If SYSSR4 RAREAS 1 FLSCR1 BAREA 0 Code area 0x0000 0x003F 0x0040 0xXXXX 0x1000 0xFFFF 0x0000 0xFFFF SFR Data area If SYSSR4 RAREAS 0 FLSCR1 BAREA 1 If SYSSR4 RAREAS 1 FLSCR1 BAREA 1 Code area RAM In serial PROM mode Note XXXXH is end of RAM address BOOTROM 0x0000 0x003F 0x0040 0xXXXX 0x1000 0x17FF 0...

Page 325: ...f interrupt vector a flash standby reset occurs after an interrupt is gener ated 21 2 6 Port input control register SPCR PIN0 PIN1 In serial PROM mode the input levels of all ports except the ports RXD0 and TXD0 used in serial PROM mode are physically fixed after a reset is released This is designed to prevent a penetration current from flow ing through unused ports port inputs and functional peri...

Page 326: ... until the same data is read from the flash memory During the write operation bit 6 is reversed each time a read is performed Note 1 To rewrite data to addresses in the flash memory where data including 0xFF is already written make sure that you erase the existing data by performing a sector erase or chip erase before writing data Note 2 The data and code areas become mirror areas As you access th...

Page 327: ... then specify either 0x8000 or 0x8FFF as the 6th bus write cycle The sector erase command is effective only in MCU and serial PROM modes and it cannot be used in parallel PROM mode The time needed to erase 4 kbytes is 30 ms maximum The next command sequence cannot be executed if an ongoing erase operation is not completed To check the completion of the erase operation perform read opera tions twic...

Page 328: ...ting is being made bit 6 is reversed each time a read is performed 21 4 Toggle Bit D6 After the flash memory write the chip erase and the security program command sequence are executed the value of the 6th bit D6 in data read by a read operation is reversed each time a read is performed This bit reversal can be used as a software mechanism for checking the completion of each operation Normally per...

Page 329: ...erial interface UART or SIO it is not necessary to operate the control regis ter for the user For details of the serial PROM mode see Serial PROM Mode To access the flash memory in serial PROM mode by using a user specific program or peripheral functions other than UART and SIO it is necessary to execute a control program in the RAM area by using the RAM loader command of the serial PROM mode How ...

Page 330: ...et a nonmaskable interrupt vector inside the RAM area step 3 LD HL 0x01FC Set INTUNDEF and INTSWI interrupt vectors LDW HL sINTSWI LD HL 0x01F8 Set INTWDT interrupt vector LDW HL sINTWDT Sector erase and write process LD HL 0xF555 Variable for command sequence LD DE 0xFAAA Variable for command sequence Sector erase process step 5 LD C 0x00 Set upper address LD IX 0xE000 Set middle and lower addres...

Page 331: ...uction is gener ated in the xth bus write cycle instructions must be arranged in such a way that they are generated at intervals of three or more machine cycles machine cycles are counted from when the last xth bus write cycle is generated to when each instruction is generated Three NOP instructions are normally used If the interval between instructions is short the toggle bit does not operation c...

Page 332: ...D to 0y010 and FLSCR1 FAREA to 0y00 set 0xD5 on FLSCR2 CR1EN This disables the execution of the command sequence and returns FAREA to the initial state of mapping 10 Generate the RET instruction to return to the flash memory 11 Invoke the write program in the RAM area by generating a CALL instruction 12 Set FLSCR1 FLSMD to 0y101 and make the appropriate FLSCR1 FAREA setting to specify the area are...

Page 333: ...and RVCTR to 1 LD SYSCR4 0xD4 Enable Code Sector erase and write process LD HL 0xF555 Variable for command sequence LD DE 0xFAAA Variable for command sequence Sector erase process step 5 LD C 0x00 Set upper addresses LD IX 0xE000 Set middle and lower addresses CALL sRAMStartAdd Perform a sector erase 0xE000 Write process step 11 LD C 0x00 Set upper addresses LD IX 0xE500 Set middle and lower addre...

Page 334: ...ed Three NOP instructions are normally used If the interval between instructions is short the toggle bit does not operation correctly sLOOP1 LD A IX steps 8 14 CMP A IX J NZ sLOOP1 Loop until the read values become the same LD FLSCR1 0x40 Disable the execution of command sequence steps 9 and 15 LD FLSCR2 0xD5 Reflect the FLSCR1 setting RET Return to flash memory Address conversion process steps 6 ...

Page 335: ...x00 Address where data is written bit 16 LD WA HL Address where data is written bits 15 to 0 LD E IY Data to be written LD SP 0xD5 Enable Code CALL BTWrite Write data to the flash memory 1 byte INC IY Increment flash address INC HL Increment RAM address CMP L 0x00 Finish 256 byte write J NZ sLOOP1 Return to sLOOP1 if the number of bytes is less than 256 End process LD FLSCR1 0x40 Set BAREA to 0 LD...

Page 336: ...21 Flash Memory 21 4 Toggle Bit D6 TMP89FM42 Note 1 Make sure that you set the C register to 0x00 LD FLSCR2 0xD5 ...

Page 337: ...TMP89FM42 21 6 Revision History Rev Description RA003 Figure 21 2 Show Hide Switching for BOOTROM and RAM Revised from WDTCR1 RAREA to SYSSR4 RAREAS ...

Page 338: ...21 Flash Memory 21 4 Toggle Bit D6 TMP89FM42 ...

Page 339: ... and RESET pin In serial PROM mode communication is performed via the UART or SIO 22 2 Security In serial PROM mode two security functions are provided to prevent illegal memory access attempts by a third party password and security program functions For more security related information refer to 22 12 Security Table 22 1 Operating Range in Serial PROM Mode Parameter Min Max Unit Power supply volt...

Page 340: ...Output Serial PROM mode control serial data output See note 1 TXD0 SO0 P20 RXD0 SI0 Input Serial PROM mode control serial data input RXD0 SI0 P21 RESET Input Serial PROM mode control RESET MODE Input Serial PROM mode control MODE SCLK0 Input Serial clock input if SIO is used These ports are in the high impedance state in the serial PROM mode If the UART is used the port input is physically fixed t...

Page 341: ...s using the UART the control of the SCLK0 pin is unnecessary Note 2 For information on other pin settings refer to Table 22 3 Pin Functions in Serial PROM Mode VDD VDD SCLK0 RXD0 P21 TXD0 P20 RESET MODE External control Pull up resistors XIN XOUT VSS GND TMP89FM42 4 5 V to 5 5 V ...

Page 342: ...M mode disconnect the circuit by using a jumper etc Note 3 For information on other pin settings refer to Table 22 3 Pin Functions in Serial PROM Mode VDD If UART is used Serial PROM mode MCU mode VDD MODE RXD0 P21 TXD0 P20 RESET PC control Pull up resistors Level converter XIN XOUT VSS GND External control board Target board RC power on reset circuit RESET control Other parts Note 1 Note 2 VDD If...

Page 343: ...efer to 22 14 1 Reset timing 1 Supply power to the VDD pin 2 Set the RESET and MODE pins to low 3 Set the RXD0 SI0 P21 and TXD0 SO0 P20 pins to high 4 Wait until the power supply and clock oscillation stabilize 5 Set the RESET and MODE pins from low to high 6 Input the matching data 0x86 or 0x30 to the RXD0 SI0 P21 pins after the setup period has elapsed ...

Page 344: ...gressed to a near completion state or if it has been completed the SO0 pin out puts the H level The external controller must check the status of the SO0 pin before it starts to supply a serial clock For information on the communication timings of each operation command refer to 1 11 AC Characteris tics SIO 22 6 2 UART communication Baud rate 9600 to 128000 bps automatic detection Data length 8 bit...

Page 345: ...sable Baud Rates as a General Guideline 9600 bps 19200 bps 38400 bps 57600bps 115200 bps 128000 bps 10 MHz Ο Ο Ο Ο Ο Ο 8 MHz Ο Ο Ο Ο Ο Ο 7 3728 MHz Ο Ο Ο Ο Ο 6 144 MHz Ο Ο Ο Ο 6 MHz Ο Ο Ο Ο Ο Ο 5 MHz Ο Ο Ο 4 9152 MHz Ο Ο Ο Ο 4 19 MHz Ο Ο Ο Ο 4 MHz Ο Ο Ο Ο Ο Ο 2 MHz Ο Ο Ο Ο 1 MHz Ο Ο Ο ...

Page 346: ...fter called the 0xF0 command is executed BOOTROM automatically converts addresses Therefore as the address of flash memory specify an address equivalent to that specified in MCU mode if FLSCR1 BAREA 0 namely 0x8000 through 0xFFFF Figure 22 3 Memory Mapping 22 8 Operation Commands In serial PROM mode the commands shown in Table 22 5 are used After a reset is released the TMP89FM42 goes into a stand...

Page 347: ...roller so that it transmits the address in memory where a read starts as well as the number of bytes After outputting the number of data equal to the number of bytes the TMP89FM42 calculates the check sums of the output data and returns the calculation results If the security program is enabled the flash memory read command cannot be executed In this case execute Chip Erase beforehand by using the...

Page 348: ...gh 0xFFFF are calculated and the calcula tion results are returned 6 Product ID code output code This is a code output used to identify a product The output code consists of information on the ROM area and on the RAM area respectively The external controller reads this code to identify the product to which data is to be written 7 Flash memory status output code The status of 0xFFE0 through 0xFFFF ...

Page 349: ...ror No data transmitted 3rd byte 4th byte Matching data 2 0x79 or 0xCF Baud rate after adjustment Baud rate after adjustment OK Echo back data 0x79 or 0xCF Error No data transmitted 5th byte 6th byte Operation command data 0xF0 Baud rate after adjustment Baud rate after adjustment OK Echo back data 0xF0 Error 0xA1 3 0xA3 3 0x63 3 note 1 7th byte 8th byte Password count storage address bit 23 to 16...

Page 350: ...executed and the security program in flash memory is disabled Therefore to disable the security program in flash memory execute Chip Erase not Sector Erase Erase area specification data data at n th 2 bytes 7 6 5 4 3 2 1 0 ERASEC ERASEC Erase area start address 0x00 Reserved 0x01 Reserved 0x02 Reserved 0x03 Reserved 0x04 Reserved 0x05 Reserved 0x06 Reserved 0x07 Reserved 0x08 0x8000 0x8FFF 0x09 0x...

Page 351: ... Erase is performed on an area where flash memory does not exist the TMP89FM42 stops communication and goes into an idle state Note 2 If Reserved data is transmitted the TMP89FM42 stops communication and goes into an idle state ...

Page 352: ...No data transmitted 5th byte 6th byte Operation command data 0x30 Baud rate after adjustment Baud rate after adjustment OK Echo back data 0x30 Error 0xA1 3 0xA3 3 0x63 3 note 1 7th byte 8th byte Password count storage address 23 to 16 Baud rate after adjustment Baud rate after adjustment OK No data transmitted Error No data transmitted 9th byte 10th byte Password count storage address 15 to 08 Bau...

Page 353: ... the TMP89FM42 by using the RESET pin and restart the serial PROM mode Note 6 If all data in flash memory are the same data make sure that you never write data to the address 0xFFE0 through 0xFFFF If data is written to this address a password error occurs and the subsequent operations cannot be performed Note 7 The n th 2 byte is a flag for detecting an overwrite If memory contents at an address w...

Page 354: ...yte 14th byte Password comparison start address 23 to 16 Baud rate after adjustment Baud rate after adjustment OK No data transmitted Error No data transmitted 15th byte 16th byte Password comparison start address 15 to 08 Baud rate after adjustment Baud rate after adjustment OK No data transmitted Error No data transmitted 17th byte 18th byte Password comparison start address 07 to 00 Baud rate a...

Page 355: ...s into an idle state Therefore if a password error occurs initialize the TMP89FM42 by using the RESET pin and restart the serial PROM mode Note 5 If a communication error occurs during the transfer of a password address or a password string the TMP89FM42 stops communication and goes into an idle state Therefore when a password error occurs initialize the TMP89FM42 by using the RESET pin and restar...

Page 356: ...after adjustment OK Echo back data 0x79 or 0xCF Error No data transmitted 5th byte 6th byte Operation command data 0x60 Baud rate after adjustment Baud rate after adjustment OK Echo back data 0x60 Error 0xA1 3 0xA3 3 0x63 3 note 1 7th byte 8th byte Password count storage address 23 to 16 Baud rate after adjustment Baud rate after adjustment OK No data transmitted Error No data transmitted 9th byte...

Page 357: ... the TMP89FM42 stops communication and goes into an idle state Therefore if a password error occurs initialize the TMP89FM42 by using the RESET pin and restart the serial PROM mode Note 6 If a communication error occurs during the transfer of a password address or a password string the TMP89FM42 stops communication and goes into an idle state Therefore when a password error occurs initialize the T...

Page 358: ...r to TMP89FM42 Baud rate Transfer data from TMP89FM42 to the external controller BOOT ROM 1st byte 2nd byte Matching data 1 0x86 or 0x30 Automatic adjustment Baud rate after adjustment Automatic baud rate adjustment OK Echo back data 0x86 or 0x30 Error No data transmitted 3rd byte 4th byte Matching data 2 0x79 or 0xCF Baud rate after adjustment Baud rate after adjustment OK Echo back data 0x79 or ...

Page 359: ...er adjustment 0x03 Length of address 3 bytes 10th byte Baud rate after adjustment 0xFD Reserved 11th byte Baud rate after adjustment 0x00 Reserved 12th byte Baud rate after adjustment 0x00 Reserved 13th byte Baud rate after adjustment 0x00 Reserved 14th byte note 2 0x80 ROM size code 15th byte Baud rate after adjustment 0x01 ROM block count 1 block 16th byte note 3 Baud rate after adjustment 0x00 ...

Page 360: ...shown here does not include the work area used by BOOTROM it is smaller than the size of a RAM built into an actual product Table 22 13 ROM Size Code 14th Byte 7 6 5 4 3 2 1 0 ROMSIZE 0 0 0 TMP89FM42 specified value 1000 0000 ROMSIZE Data on the flash memory size 00010 4Kbytes 00100 8Kbytes 01000 16Kbytes 10000 32Kbytes 11000 48Kbytes 11110 60Kbytes 10001 96Kbytes 11111 124Kbytes Read only ...

Page 361: ... data transmitted 3rd byte 4th byte Matching data 2 0x79 or 0xCF Baud rate after adjustment Baud rate after adjustment OK Echo back data 0x79 or 0xCF Error No data transmitted 5th byte 6th byte Operation command data 0xC3 Baud rate after adjustment Baud rate after adjustment OK Echo back data 0xC3 Error 0xA1 3 0xA3 3 0x63 3 note 1 7th byte Baud rate after adjustment 0x3A Start mark 8th byte Baud r...

Page 362: ...1F see information below 4th Reserved 0x00 5th Reserved 0x00 6th Reserved 0x00 7th Checksum of transfer data complement of 2 of the sum total of 3rd through 6th bytes If 3rd data is 0x00 0x00 If 3rd data is 0x01 0xFF If 3rd data is 0x02 0xFE If 3rd data is 0x03 0xFD Status code 1 7 6 5 4 3 2 1 0 EPFC DAFC RPENA BLANK Initial value EPFC Password string judgment when the flash memory erase command i...

Page 363: ...oes into an idle state RPENA BLANK EPFC DAFC Flash memory overwrite command flash memory read command and RAM loader command Flash memory SUM out put command product ID output command and status output command Flash memory erase command Flash memory security setting command Chip erase Sector erase 0 0 0 0 Ο Ο Ο 1 0 0 0 Ο Ο 0 1 0 Pass Ο Ο Pass 1 Pass Ο Pass Pass 1 1 0 Ο Ο Pass 1 Ο Pass Pass ...

Page 364: ...m TMP89FM42 to the external controller BOOT ROM 1st byte 2nd byte Matching data 1 0x86 or 0x30 Automatic adjustment Baud rate after adjustment Automatic baud rate adjustment OK Echo back data 0x86 or 0x30 Error No data transmitted 3rd byte 4th byte Matching data 2 0x79 or 0xCF Baud rate after adjustment Baud rate after adjustment OK Echo back data 0x79 or 0xCF Error No data transmitted 5th byte 6t...

Page 365: ...0 Error No data transmitted 3rd byte 4th byte Matching data 2 0x79 or 0xCF Baud rate after adjustment Baud rate after adjustment OK Echo back data 0x79 or 0xCF Error No data transmitted 5th byte 6th byte Operation command data 0xFA Baud rate after adjustment Baud rate after adjustment OK Echo back data 0xFA Error 0xA1 3 0xA3 3 0x63 3 note 1 7th byte 8th byte Password count storage address 23 to 16...

Page 366: ...2 transmits when it detects errors Note If a password error occurs the TMP89FM42 does not transmit an error code Table 22 18 Error Codes Data transmitted Meaning of error data 0x63 0x63 0x63 Operation command error 0xA1 0xA1 0xA1 Framing error in the received data 0xA3 0xA3 0xA3 Overrun error in the received data ...

Page 367: ...4 Table 22 19 Data for which a Checksum Is Calculated Operation command Calculation data Description Flash memory erase command All data in the erased area of flash mem ory whole or part of flash memory When the sector erase is executed only the erased area is used to calculate the checksum In the case of the chip erase an entire area of the flash memory is used Flash memory write command Data in ...

Page 368: ... Intel Hex format error occurs the TMP89FM42 goes into an idle state without return ing an error code to the external controller The Intel Hex format error occurs in the following cases If the record type is other than 00h 01h or 02h If a checksum error of the Intel Hex format occurs If the data length of an extended record record type 0x02 is not 0x02 If the TMP89FM42 receives the data record aft...

Page 369: ... MCU where the password is specified The area where a password can be specified is 0x8000 through 0xFEFF in flash memory 22 12 1 2Password structure A password consists of three components PNSA PCSA and a password string Figure 22 4 shows the password structure example of a transmitted password PNSA password count storage address A 3 byte address is specified in the area 0x8000 through 0xFEFF The ...

Page 370: ...5 0x08 0xF012 0xF107 0xF108 Flash memory 0xF109 0xF10A 0xF10B 0xF10C 0x00 0xF0 0x12 0xF1 0x00 0x07 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 PNSA PCSA Password string 0x06 0x07 0xF10D 0xF10E 0x08 is the number of passwords 8 bytes Compare Example PNSA 0xF012 PCSA 0xF107 0x01 0x02 0x03 0x04 0x05 0x06 0x07 and 0x08 are assumed RXD SI pin MCU ...

Page 371: ...o password authentication is performed To execute some special operation com mands however PNSA and PCSA are still required a password string is not required even if a product is blank In this case the addresses defined in Table 22 21 must be selected as PNSA and PCSA Whether a product is blank or non blank can be confirmed by executing the status output command The operation commands that require...

Page 372: ... product receives the Intel Hex format data immediately after receiving PCSA it does not receive password strings In this case the subsequent processing is performed correctly because the TMP89FM42 keeps ignoring incoming data until the start mark 0x3A in the Intel Hex format is detected even if the external controller transmits the dummy password string However if the dummy password string contai...

Page 373: ...ided prohibiting the system startup by using an option code and starting the system by password authentication 22 12 2 1How the security program functions With the TMP89FM42 you can control the read of flash memory by writing protection related informa tion to a specially designed memory Because protection related information is written to this specially designed memory no user memory resource are...

Page 374: ... are imposed on operation commands related to memory access and the startup of OCD The security program should be usually enabled at the time of shipment If there is the possibility that the OCD may be used by keeping the contents of memory intact it is possible to directly start the OCD by setting the OCD security program free code DAFC_OP and thereby skipping the security program check the passw...

Page 375: ...e password authentication and OCD security program authentication are disabled Vector Section romdata abs 0xFFFA DB DB 0xFF 0xFF Cancel the password string during the erase operation EPFC_OP Permit access when the OCD is started DAFC_OP ...

Page 376: ...ays enable the security program to protect ROM data Table 22 23 Option Codes and Recommended Security Program Settings Device status Serial PROM mode Parallel PROM mode OCD EPFC_OP 0xFFFA DAFC_OP 0xFFFB Security Program Memory read Erase Memory read Erase At the time of debug ging during software development 0xFF 0xFF Disable Password string required Possible Possible Possible Can be used In quant...

Page 377: ...d loop Blank check Password check NG OK Closed loop Blank check Password check NG OK Disabled Enabled Receive data 40H flash memory read command Receive data 0xF0 flash memory erase command Transmit data 0xD0 Receive data D0H mask ROM emulation setting command Blank check Enable Security Program Closed loop Password check NG OK Receive data 0xFA Security Program enable command Transmit data 0xFA T...

Page 378: ... data number of read bytes to when it transmits memory data CMrd Approx 430 430 µs 43 µs Time from when MCU receives data mask ROM emulation setting data to when it echoes back CMem2 Approx 420 420 µs 42 µs Time required to enable the security program CMrp Approx 1080 1 08 ms 108 µs Table 22 25 UART Timing 2 Parameter Symbol Clock frequency fcgck Minimum required time At fcgck 1 MHz At fcgck 10 MH...

Page 379: ...F0 Figure 22 7 Flash Memory Erase Command RXD 0x86 RXsup RSsup CMeb1 CMtr1 0x79 TXD RESET MODE VDD 0x86 0x79 CMeb2 CMeb3 Operation command CMtr2 CMtr3 23 16 15 8 PNSA 7 0 15 8 7 0 RXD TXD 0xF0 CMtr3 23 16 15 8 PCSA Password string Area to be erased Checksum 7 0 RXD TXD CMnx CMfsm Next command ...

Page 380: ...16 15 8 PNSA 7 0 15 8 7 0 RXD TXD 0x30 CMtr3 23 16 15 8 PCSA Password string IntelHex Checksum Overwrite detection IntelHex End Record 7 0 0x3A RXD TXD CMwr CMnx CMfsm Next command 0x00 0x00 0x01 0xFF 0x55 or 0xAA 23 16 15 8 PNSA 7 0 15 8 7 0 RXD TXD 0x40 CMtr3 23 16 15 8 PCSA Password string Read start address Checksum Memory data 7 0 23 16 15 8 7 0 Number of read bytes 23 16 15 8 7 0 RXD TXD CMn...

Page 381: ...t ID code output command 0xC0 Figure 22 12 Product ID Code Output Command 23 16 15 8 PNSA 7 0 15 8 7 0 RXD TXD 0x60 CMtr3 23 16 15 8 PCSA Password string IntelHex Checksum IntelHex End Record 7 0 0x3A RXD TXD CMnx CMrsm Next command 0x00 0x00 0x01 0xFF CMfsm RXD TXD 0x90 0x55 or 0xAA FF check Checksum CMnx 15 8 7 0 Next command RXD TXD 0xC0 Product ID code CMnx Next command ...

Page 382: ... 14 9Mask ROM emulation setting command 0xD0 Figure 22 14 Mask ROM Emulation Setting Command 22 14 10Flash memory security setting command 0xFA Figure 22 15 Flash Memory Security Setting Command RXD TXD 0xC3 Status code CMnx Next command 23 16 15 8 PNSA 7 0 0xFB RXD TXD 0xFA CMtr3 23 16 15 8 PCSA Password string Echo back 7 0 RXD TXD CMnx CMrp Next command ...

Page 383: ...on History Rev Description RA002 Added P20 and P21 description to TXD0 and RXD0 pin Table 22 24 UART Timing 1 Table 22 25 UART Timing 2 Deleted VDD and Topr condition These condition is defined in Electrical Characteristics ...

Page 384: ...22 Serial PROM Mode 22 15 Revision History TMP89FM42 ...

Page 385: ...active memory and to overwrite active memory are provided Built in flash memory can be erased and written 23 2 Control Pins The on chip debug function uses two pins for communication and four pins for power supply reset and mode con trol The pins used for the on chip debug function are shown in Table 23 1 Ports P20 and P21 are used as communication control pins of the on chip debug function If the...

Page 386: ... it must be dis connected using a jumper switch etc Note 3 The power supply voltage VDD must be provided by a target system The VDD pin is connected to the emulator so that the level of voltage appropriate for driving communication pins can be obtained by using the power supply of a target system The connection of the VDD pin is for receiving the power supply voltage not for supplying it from the ...

Page 387: ...s are shown below Control pin I O Circuitry Remarks XIN XOUT Input Output Refer to the P0 ports in the chapter of Input Output Ports XTIN XTOUT Input Output Refer to the P0 ports in the chapter of Input Output Ports RESET Input Refer to the P1 ports in the chapter of Input Output Ports MODE Input R 100 Ω typ R ...

Page 388: ...24 Input Output Circuit 24 1 Control Pins TMP89FM42 ...

Page 389: ...uding P23 and P24 P4 P7 P8 P9 PB tri state port 0 3 to VDD 0 3 V VIN2 P23 P24 sink open drain port 0 3 to VDD 0 3 VIN3 AIN0 to AIN7 analog input voltage 0 3 to AVDD 0 3 Output voltage VOUT1 0 3 to VDD 0 3 V Output current per pin IOUT1 P0 P1 P2 excluding P23 and P24 P4 P7 P8 P9 PB tri state port 1 8 mA IOUT2 P0 P1 P2 P4 P9 pull up resistor 0 4 IOUT3 P0 P1 P2 P4 P74 to P77 P8 P9 tri state port 3 2 ...

Page 390: ... this device ensure that the operating conditions for the device are always adhered to 25 2 1 MCU mode Flash Programming or erasing Figure 25 1 Clock gear fcgck and High frequency clock fc VSS 0 V Topr 10 to 40 C Parameter Symbol Pins Condition Min Max Unit Supply voltage VDD NORMAL1 2 modes 4 5 5 5 V Input high level VIH1 MODE pin VDD 4 5 V VDD 0 70 VDD VIH2 Hysteresis input VDD 0 75 Input low le...

Page 391: ...ysteresis input VDD 0 75 VIH3 VDD 4 5 V VDD 0 90 Input low level VIL1 MODE pin VDD 4 5 V 0 VDD 0 30 VIL2 Hysteresis input VDD 0 25 VIL3 VDD 4 5 V VDD 0 10 Clock frequency fc XIN XOUT VDD 2 2 to 5 5 V 1 0 8 0 MHz VDD 2 7 to 5 5 V 1 0 10 0 fcgck VDD 2 2 to 5 5 V 0 25 2 0 VDD 2 7 to 5 5 V 4 2 VDD 4 3 to 5 5 V 10 0 fs XTIN XTOUT VDD 2 2 to 5 5 V 30 0 34 0 kHz 5 5 4 3 2 7 0 250 2 1 2 4 4 2 4 2 10 MHz G...

Page 392: ... Max Unit Supply voltage VDD NORMAL1 2 modes 4 5 5 5 V Input high voltage VIH1 MODE pin VDD 4 5 V VDD 0 70 VDD VIH2 Hysteresis input VDD 0 75 Input low voltage VIL1 MODE pin VDD 4 5 V 0 VDD 0 30 VIL2 Hysteresis input VDD 0 25 Clock frequency fc XIN XOUT VDD 4 5 V 1 0 10 0 MHz fcgck 0 25 10 0 5 5 4 5 0 250 1 10 MHz Gear clock fcgck frequency range V 5 5 4 5 MHz High frequency clock fc frequency ran...

Page 393: ...P5 P7 P8 P9 PB IIN3 RESET STOP Input resistance RIN2 RESET pull up VDD 5 5 V VIN VMODE 0 V 100 220 500 kΩ RIN3 P0 P1 P2 excluding P23 and P24 P4 P9 pull up 30 50 100 Output leakage current ILO1 P23 P24 skin open drain port VDD 5 5 V VOUT 5 5 V 2 µA ILO2 P0 P1 P2 excluding P23 and P24 P4 P5 P7 P8 P9 PB tri state port VDD 5 5 V VOUT 5 5 V 0 V 2 Output high voltage VOH Except P23 P24 XOUT XTOUT VDD 4...

Page 394: ...25 5 Note 9 The circuit of a power supply must be designed such as to enable the supply of a peak current This peak current causes the supply voltage in the device to fluctuate Connect a bypass capacitor of about 0 1 µF near the power supply of the device to stabilize its operation VSS 0 V Topr 40 to 85 C Parameter Symbol Pins Condition Min Typ Max Unit Supply current in NORMAL 1 2 modes Note 7 ID...

Page 395: ...ounter PC n 1 n 2 n 3 1 machine cycle MCU current I mA DDP P Typical current Momentary flash current Maximum current Sum of average momentary flash current and MCU current Internal write signal TBD TSCE Last write cycle of each of the Byte Program Security Program Chip Erase and Sector Erase I mA DDEW Internal data bus Program counter PC 1 machine cycle ...

Page 396: ...F Power supply current of analog refer ence voltage IREF VDD AVDD VAREF 5 5 V VSS 0 0 V 0 6 1 0 mA Non linearity error VDD AVDD VAREF 5 0 V VSS 0 0V 3 LSB Zero point error 3 Full scale error 3 Total error 3 VSS 0 0 V 2 7 V VDD 4 5 V Topr 40 to 85 C Parameter Symbol Condition Min Typ Max Unit Analog reference voltage Power sup ply voltage of analog control circuit VAREF AVDD VDD V Analog input volt...

Page 397: ...until an oscillating circuit stabilizes some errors may be included in the warming up time Note 3 Boost the power supply voltage such that tVDD becomes smaller that tPWUP VSS 0 V Topr 40 to 85 C Symbol Parameter Min Typ Max Unit VPROFF Power on reset releasing voltageNote 1 85 2 02 2 19 V VPRON Power on reset detecting voltageNote 1 75 1 85 1 95 tPROFF Power on reset releasing response time 0 01 0...

Page 398: ...ot fulfill its functions due to the fluc tuations in the power supply voltage VDD VSS 0 V Topr 40 to 85 C Symbol Parameter Min Typ Max Unit tVLTOFF Voltage detection releasing response time 0 01 0 1 ms tVLTON Voltage detecting detection response time 0 01 0 1 tVLTPW Voltage detecting minimum pulse width 1 0 Level of detected voltage Operating voltage Power supply voltage VDD Signal to request the ...

Page 399: ...l Condition Min Typ Max Unit Machine cycle time tcy NORMAL1 2 modes 0 100 4 µs IDLE0 1 2 modes SLOW1 2 modes 117 6 133 3 SLEEP0 1 modes High level clock pulse width tWCH For external clock operation XIN input fc 10 0 MHz 50 0 ns Low level clock pulse width tWCL High level clock pulse width tWSH For external clock operation XTIN input fs 32 768 kHz 15 26 µs Low level clock pulse width tWSL VSS 0 V ...

Page 400: ...tion XTIN input fs 32 768 kHz 15 26 µs Low level clock pulse width tWSL VSS 0 V VDD 4 5 V to 5 5 V Topr 10 to 40 C Parameter Symbol Condition Min Typ Max Unit Machine cycle time tcy NORMAL1 2 modes 0 100 4 µs IDLE0 1 2 modes SLOW1 2 modes 117 6 133 3 SLEEP0 1 modes High level clock pulse width tWCH For external clock operation XIN input fc 10 0 MHz 50 0 ns Low level clock pulse width tWCL High lev...

Page 401: ...oard patterns please be sure to evaluate operation on the board on which the device will actually be mounted Note 2 The product numbers and specifications of the resonators supplied by Murata Manufacturing Co Ltd are subject to change For up to date information please refer to the following http www murata com XTIN XTOUT C2 C1 XIN XOUT C2 C1 1 High frequency oscillation 2 Low frequency oscillation...

Page 402: ...ing time 5 seconds Number of times once R type flux used 2 When using the Sn 3 0Ag 0 5Cu solder bath Solder bath temperature 245 C Dipping time 5 seconds Number of times once R type flux used Note The pass criteron of the above test is as follows Solderability rate until forming 95 When using the device oscillator in places exposed to high electric fields such as cathode ray tubes we recommend ele...

Page 403: ...imum value of the operation frequency is changed from 8MHz to 10MHz Added figure for Clock gear fcgck and High frequency clock fc 25 4 AD Conversion Characteristics Fixed spec RA002 25 5 Power on Reset Circuit Characteristics Revised table IPWUP Unit from ms to s ...

Page 404: ...25 Electrical Characteristics 25 11 Revision History TMP89FM42 ...

Page 405: ...TMP89FM42 26 Package Dimensions 0 37 12 0 0 2 10 0 0 2 12 0 0 2 10 0 0 2 0 6 0 15 0 25 0 1 4 5 0 0 5 5 0 1 1 6MAX 0 05 1 4 0 05 0 08 0 07 0 2 0 8 1 0TYP LQFP44 P 1010 0 80B Rev 01 Unit mm ...

Page 406: ...26 Package Dimensions TMP89FM42 ...

Page 407: ...y with version updates The recent advances in CMOS LSI production technology have been phenomenal and microcomputer systems for LSI design are constantly being improved The products described in this document may also be revised in the future Be sure to check the latest specifications before using Toshiba is developing highly integrated high performance microcomputers using advanced MOS production...

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