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TMP89FM42
RA001
A software reset is generated by writing "10" and then "01" to SBI0CR2<SWRST>.
After a software reset is generated, the serial bus interface circuit is initialized and all the bits of SBI0CR2
register, except SBI0CR2<SBIM> and the SBI0CR1, I2C0AR<SA> and SBI0SR2 registers, are initialized.
18.4.11Arbitration lost detection monitor
Since more than one master device can exist simultaneously on a bus, a bus arbitration procedure is imple-
mented in order to guarantee the contents of transferred data.
Data on the SDA line is used for bus arbitration of the I
2
C bus.
The following shows an example of a bus arbitration procedure when two master devices exist simulta-
neously on a bus. Master 1 and Master 2 output the same data until point "a". After that, when Master 1 outputs
"1" and Master 2 outputs "0", since the SDA line of a bus is wired AND, the SDA line is pulled down to the
low level by Master 2. When the SCL line of a bus is pulled-up at point "b", the slave device reads data on the
SDA line, that is data in Master 2. Data transmitted from Master 1 becomes invalid. The state in Master 1 is
called "arbitration lost". A master device which loses arbitration releases the SDA pin and the SCL pin in order
not to effect data transmitted from other masters with arbitration. When more than one master sends the same
data at the first word, arbitration occurs continuously after the second word.
Figure 18-12 Arbitration Lost
The serial bus interface circuit compares levels of a SDA line of a bus with its SDA pin at the rising edge of
the SCL line. If the levels are unmatched, arbitration is lost and SBI0SR2<AL> is set to "1".
When SBI0SR2<AL> is set to "1", SBI0CR2<MST> and SBI0CR2<TRX> are cleared to "0" and the mode
is switched to a slave receiver mode. Thus, the serial bus interface circuit stops output of clock pulses during
data transfer after the SBI0SR2<AL> is set to "1". After the data transfer is completed, SBICR2<PIN> is
cleared to "0" and the SCL pin is pulled down to the low level.
SBI0SR2<AL> is cleared to "0" by writing data to the SBI0DBR, reading data from the SBI0DBR or writing
data to the SBI0CR2.
a
b
SCL (Bus)
SDA pin (Master 1)
SDA pin (Master 2)
SDA (Bus)
The SDA pin becomes "1" after losing arbitration.
Summary of Contents for TLCS-870/C1 Series
Page 1: ...8 Bit Microcontroller TLCS 870 C1 Series TMP89FM42 查询TMP89FM42供应商 捷多邦 专业PCB打样工厂 24小时加急出货 ...
Page 3: ...Revision History Date Revision 2007 10 25 1 First Release 2007 11 3 2 Contents Revised ...
Page 4: ......
Page 14: ......
Page 18: ...1 3 Block Diagram TMP89FM42 1 3 Block Diagram Figure 1 2 Block Diagram ...
Page 22: ...1 4 Pin Names and Functions TMP89FM42 ...
Page 60: ...2 CPU Core 2 5 Revision History TMP89FM42 ...
Page 76: ...3 Interrupt Control Circuit 3 8 Revision History TMP89FM42 ...
Page 86: ...4 External Interrupt control circuit 4 3 Function TMP89FM42 ...
Page 102: ...7 Voltage Detection Circuit 7 5 Revision History TMP89FM42 ...
Page 126: ...8 I O Ports 8 3 I O Port Registers TMP89FM42 Note 2 i 0 to 1 ...
Page 136: ...8 I O Ports 8 5 Revision History TMP89FM42 ...
Page 142: ...9 Special Function Registers 9 3 SFR3 0x0E40 to 0x0EFF TMP89FM42 ...
Page 146: ...10 Low Power Consumption Function for Peripherals TMP89FM42 ...
Page 149: ...TMP89FM42 11 3 Revision History Rev Description RA001 Deleted SLEEP2 description ...
Page 150: ...11 Divider Output DVO 11 3 Revision History TMP89FM42 ...
Page 220: ...15 Real Time Clock RTC 15 4 Real Time Clock Operation TMP89FM42 ...
Page 250: ...16 Asynchronous Serial Interface UART 16 15 Revision History TMP89FM42 ...
Page 302: ...18 Serial Bus Interface SBI 18 7 Revision History TMP89FM42 ...
Page 338: ...21 Flash Memory 21 4 Toggle Bit D6 TMP89FM42 ...
Page 384: ...22 Serial PROM Mode 22 15 Revision History TMP89FM42 ...
Page 388: ...24 Input Output Circuit 24 1 Control Pins TMP89FM42 ...
Page 404: ...25 Electrical Characteristics 25 11 Revision History TMP89FM42 ...
Page 406: ...26 Package Dimensions TMP89FM42 ...
Page 408: ......