Toshiba Tecra 710CDT, Maintenance Manual

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710CDT/720CDT
Tag RAM:
- 32 KB (only 8 KB is used)
- One 32K x 8-bit asynchronous SRAM chip
- 3.3 volt operation
- 15 ns access time
The level-2 cache uses direct mapping, utilizing a write-through policy.
❑
Standard RAM
16 MB, eight 1M x 16-bit EDO DRAM chips
3.3 volt operation
No parity bit
60 ns access time
64-bit width data transfer
❑
BIOS ROM (Flash EEPROM)
256 KB, one 256K x 8-bit chip
- 128 KB are used for system BIOS
- 64 KB are used for VGA-BIOS
- 8 KB are used for plug and play data area
- 8 KB are used for password security
- 16 KB are used for boot strap
- 32 KB are reserved
5 volt operation
120 ns access time
8-bit width data transfer
❑
Optional memory
One expansion memory slot for 8, 16, 32, 64, and 128MB memory modules, which
consist of 1M x 16-bit chips (8, 16, 32MB) and 4M x 16-bit chips (64, 128MB).
EDO DRAM is used
3.3 volt operation
No parity bit
60 ns access time
64-bit width data transfer
❑
Video RAM
2 MB, four 256K x 16-bit EDO DRAM chips
5 volt operation
60 ns access time
❑
System controller Gate Array
This gate array has the following functions:
- CPU interface/control
- Level-2 cache memory control
- DRAM control
- PCI master/slave interface
- Write buffer (CPU-DRAM, CPU-PCI, PCI-DRAM)