Verdin Carrier Board Design Guide
Preliminary
– Subject to Change
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3.5.5.8
Capacitive Coupling
Some high-speed signals allow (or require) capacitive coupling. Capacitive coupling blocks all DC
current and eliminates backfeeding caused by a DC offset of high-speed signals. Most high-speed
interfaces and differential clocks (e.g., LVPECL, CML) use capacitive coupling nowadays. Typical
signals using capacitive coupling are PCIe, SATA, DisplayPort, and the SuperSpeed signals of USB.
Some of these signals are featuring the coupling capacitors already on the Verdin module. Please
read the interface guidelines in section 2 of this document carefully for understanding whether
coupling capacitors are required on the carrier board or not.
Figure 81: Capacitive coupled signals
3.5.5.9
Non-Backfeeding Buffer
Placing an additional buffer in the signal path can prevent backfeeding. The buffer needs to be
powered from the same domain as the rail of the input. If the Verdin module is the signal input,
using the PWR_1V8_MOCI as the buffer's power supply is the right approach (if the
PWR_1V8_MOCI can provide enough current). Noteworthy, the buffer should not have an ESD
protection circuit at its input that allows for backfeeding. Otherwise, the signal would back feed to
the PWR_1V8_MOCI, and the whole circuit would lose its purpose.
Figure 82: Non-backfeeding buffer
Peripheral
SoC
IO Rail (off)
RX
Module Pin
Peripheral Rail (on)
TX
0V
1.8V
0.9V DC
0V
High
Peripheral
SoC
IO Rail (off)
RX
Module Pin
Peripheral Rail (on)
TX
0V
1.8V
1.6V
0V
High
PWR_1V8_MOCI (off)
0V
