Verdin Carrier Board Design Guide
Preliminary
– Subject to Change
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2.17
General Purpose Clock Outputs
The Verdin module standard reserves two module edge connector pins as general purpose clock
outputs. One output is intended to be used for the digital audio interface while the other one is
reserved for the camera interface. The clock outputs could also be used for other purposes if not
required by the dedicated function. Please note that on some modules, the possible output
frequencies are limited. There might also be limitations due to the other clock sources that are
used in the module or the interface they are dedicated to needs to be enabled in order to be able
to enable the clock output. Read carefully the relevant datasheets.
2.17.1
Clock Output Signals
Verdin
Pin
Verdin
Signal Name
I/O
Type
Power
Rail
Description
38
I2S_1_MCLK
O
CMOS
1.8V
Clock output for the digital audio interface
91
CSI_1_MCLK
O
CMOS
1.8V
Clock output for the MIPI CSI-2 camera interface
Table 32: Clock Output Signals
2.17.2
Schematic and Layout Considerations
The clock output signals can have quite a high frequency, especially for single ended clock signals.
This could lead to major problems due to electromagnetic interferences (EMI). The clock signals
should be kept as short as possible. High slew rates of the signal can increase the EMI problems.
Therefore, it is desirable to reduce the slew rate as much as the signal quality allows it. Therefore,
series resistors should be placed close to the clock output of the module. Start with a value of 22
Ω
.
Try to increase this value until the corresponding interface fails due to the signal quality of the
clock signal. Decrease the serial resistor again in order to have a suitable margin.
Instead of using the clock output signals, some of the interfaces also allow using a different
asynchronous clock reference. For example, if the audio codec or the camera needs to be located
far away from the Verdin computer module, it might be a better solution to use an oscillator
instead of the reference clock output of the module. This oscillator can be placed close to the audio
codec or camera.
2.17.3
Unused Clock Output Signal Termination
Unused clock output signals can be left unconnected. The output should be disabled for reducing
power consumption and EMI problems.
2.18
GPIO
The Verdin form factor features 4x dedicated general-purpose input output pins (GPIO) plus
additional 2x GPIOs which are reserved for the MIPI DSI interface and additional 4x GPIOs which
are reserved for the MIPI CSI interface. Beside these 10x GPIOs, several pins can be used as GPIO
if their primary function is not in use. The Table 2 and Table 3 show an overview of the interfaces.
For carrier boards intended to provide the highest compatibility with all different Verdin modules, it
is recommended to use the 10x GPIO signals first. If additional GPIO signals are required, unused
signal pins of the interfaces that are stated as “GPIO Capable” could be used.
2.18.1
GPIO Signals
The following table contains the 10x GPIO pins available on Verdin modules. Consult the relevant
datasheet of the modules for information on the other module edge connector pins that can be
used as GPIO interface.
