1-10
Themis Computer
RES-32XR3-S for X8DTL-6/6F Installation Manual
1.3
Chipset Overview
Built upon the functionality and the capability of the 5500 platform, the RES-
32XR3-S for X8DTL-6/6F motherboard provides the performance and feature set
required for dual-processor-based high-end systems optimized for HCP/Cluster sys-
tems and intensive applications. The 5500 platform consists of the 5500 Series
(LGA 1366) processor, the 5500 (IOH-24D), and the ICH10R (South Bridge). With
the Intel QuickPath interconnect (QPI) controller built in, the 5500 platform is the
first dual-processing platform that offers the next generation point-to-point system
interconnect interface, replacing the current Front Side Bus Technology, substan-
tially enhancing system performance with increased bandwidth and scalability.
The 5500 (IOH-24D) connects to each processor through an independent Quick-Path
Interconnect (QPI) link. Each link consists of 20 pairs of unidirectional differential
lanes for transmitting and receiving in addition to a differential forwarded clock. A
full-width QPI link pair provides 84 signals. Each processor supports two QuickPath
links, one going to the other processor and the other to the 5500 (IOH-24D).
The 5500 Platform supports up to 24 PCI Express Gen2 lanes, peer-to-peer read and
write transactions. The ICH10R provides up to 4 PCI-Express ports, six SATA ports
and 7 USB connections.
In addition, the 5500 platform also offers a wide range of RAS (Reliability, Avail-
ability and Serviceability) features. These features include memory interface ECC,
x4/x8 Single Device Data Correction (SDDC), Cyclic Redundancy Check (CRC),
parity protection, out-of-band register access via SMBus, memory mirroring, and
Hot-plug support on the PCI-Express Interface.
1.3.1
Main Features of the 5500 Series Processor and the
5500 Chipset
• Four processor cores in each processor with 8MB shared cache among cores
• Two full-width Intel QuickPath interconnect links, up to 6.4 GT/s of data transfer
rate in each direction
