Texas Instruments TMS320F28004 Series, Manual

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Table 1-2. Advisories Matrix (continued)
MODULE DESCRIPTION
SILICON REVISIONS
AFFECTED
0 A B
ADC ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt Mode) is not Set Yes Yes Yes
ADC ADC: Degraded ADC Performance With ADCCLK Fractional Divider Yes Yes Yes
ADC ADC: DMA Read of Stale Result Yes Yes Yes
CLB CLB: Back-to-Back PUSH or PULL Instructions With More Than One Active High
Level Controller (HLC) Channel is not Supported Yes Yes Yes
Analog Subsystem Analog Subsystem: Software Configuration for Shared Reference Pins Yes Yes –
Analog Trim of Some TMX Devices Yes Yes –
PGA PGA: Output Filter Path is Not Supported Yes Yes –
ROM ROM: Flash API Library and FPU32 Twiddle Factor RFFT Table Not Present Yes Yes –
REVID REVID: Some TMX Revision A Devices Have an Incorrect REVID Value – Yes –
GPIO GPIO: X2/GPIO18 Pin Pullup Current During Power Up Yes Yes Yes
GPIO GPIO: Open-Drain Configuration May Drive a Short High Pulse Yes Yes Yes
GPIO GPIO: Parasitic Path to V
SS
When Maximum V
IH
is Exceeded in Input Mode – Yes –
GPIO GPIO: Pins may Drive High During Power Up Yes – –
GPIO GPIO: Signal Latch-up to V
SS
Yes – –
LIN LIN: Inconsistent Sync Field Error (ISFE) Flag/Interrupt Not Set When Sync Field is
Erroneous Yes Yes Yes
www.ti.com Usage Notes and Advisories Matrices
SPRZ439G – JANUARY 2017 – REVISED AUGUST 2022
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TMS320F28004x Real-Time MCUs Silicon Errata
Silicon Revisions B, A, 0
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