Texas Instruments TMS320F28004 Series, Manual

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Advisory BOR: VDDIO Between 2.45 V and 3.0 V can Result in Multiple XRSn Pulses
Revisions Affected 0, A, B
Details The BOR can generate repeating XRSn assertions and deassertions when the VDDIO
supply voltage is between 2.45 V and 3.0 V. It is recommended that the XRSn pin
not be
used directly as a reset to any other devices in the system.
The F28004x BOR is effective for internally holding the device in a known reset state,
even when these XRSn pulses are occurring. The device will not branch to application
code or bootloaders, and all other pins will be held in their reset state until the VDDIO
supply rises above 3.0 V.
Workarounds 1. Ignore the extra XRSn transitions during power up, power down, and BOR events.
The extra XRSn pulses will have no effect on the F28004x device operation itself.
2. If XRSn pulses would cause undesired system behavior with other system
components, then do not use XRSn to drive other devices. An external voltage
supervisor can be used for these applications.
3. For applications that need to avoid these pulses during normal power up and power
down:
a. Power up: Follow the t
VDDIO-RAMP
requirement in the Recommended Operating
Conditions table of the TMS320F28004x Real-Time Microcontrollers data sheet;
no extra XRSn low pulses will occur.
b. Power Down: To avoid any deassertion of XRSn during power down, design the
power supply so that VDDIO passes through the range from 3.0 V to 2.45 V within
25 µs. If some voltage rise on XRSn is acceptable, then the time constant of the
RC circuit implemented on XRSn can be calculated to ensure the voltage does
not rise above a system-specified threshold.
www.ti.com Silicon Revision B Usage Notes and Advisories
SPRZ439G – JANUARY 2017 – REVISED AUGUST 2022
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TMS320F28004x Real-Time MCUs Silicon Errata
Silicon Revisions B, A, 0
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