Texas Instruments TMS320F28004 Series, Manual

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Advisory ADC: Degraded ADC Performance With ADCCLK Fractional Divider
Revisions Affected 0, A, B
Details Using fractional SYSCLK-to-ADCCLK dividers (controlled by the ADCCTL2.PRESCALE
field) has been shown to cause degradation in ADC performance on this device. See
Table 3-2 .
Table 3-2. ADCCTL2 Register
REDUCED PERFORMANCE
BIT FIELD VALUE DESCRIPTION
3–0 PRESCALE 0001 ADCCLK = SYSCLK/1.5
0003 ADCCLK = SYSCLK/2.5
...
NORMAL PERFORMANCE
BIT FIELD VALUE DESCRIPTION
3–0 PRESCALE 0000 ADCCLK = SYSCLK/1.0
0002 ADCCLK = SYSCLK/2.0
...
Workaround Use even PRESCALE clock divider values. Even PRESCALE values result in integer
clock dividers which do not impact the ADC performance.
Advisory ADC: DMA Read of Stale Result
Revisions Affected
0, A, B
Details The ADCINT flag can be set before the ADCRESULT value is latched (see the t
LAT
and t
INT(LATE)
columns in the ADC Timings table of the TMS320F28004x Real-Time
Microcontrollers data sheet). The DMA can read the ADCRESULT value as soon as
3 cycles after the ADCINT trigger is set. As a result, the DMA could read a prior
ADCRESULT value when the user expects the latest result if all of the following are true:
• The ADC is in late interrupt mode.
• The ADC operates in a mode where t
INT(LATE)
occurs 3 or more cycles before t
LAT
(ADCCTL2 [PRESCALE] > 2).
• The DMA is triggered from the ADCINT signal.
• The DMA immediately reads the ADCRESULT value associated with that ADCINT
signal without reading any other values first.
• The DMA was idle when it received the ADCINT trigger.
Only the DMA reads listed above could result in reads of stale data; the following non-
DMA methods will always read the expected data:
• The ADCINT flag triggers a CLA task.
• The ADCINT flag triggers a CPU ISR.
• The CPU polls the ADCINT flag.
Workaround Trigger two DMA channels from the ADCINT flag. The first channel acts as a dummy
transaction. This will result in enough delay that the second channel will always read the
fresh ADC result.
Silicon Revision B Usage Notes and Advisories www.ti.com
32 TMS320F28004x Real-Time MCUs Silicon Errata
Silicon Revisions B, A, 0 SPRZ439G – JANUARY 2017 – REVISED AUGUST 2022
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