Advisory
PLL: PLL May Not Lock on the First Lock Attempt
Revisions Affected
0, A, B
Details
The PLL may not start properly at device power up. The PLLSTS[LOCKS] bit is set, but
the PLL does not produce a clock.
Once the PLL has started properly, the PLL can be disabled and reenabled with no issues
and will stay locked. However, the PLL lock problem could reoccur on a subsequent
power-up cycle.
If the SYSPLL has not started properly and is selected as the CPU clock source, the CPU
will stop executing instructions.
The occurrence rate of this transient issue is low. After an initial occurrence, this
issue may not be subsequently observed in the system again. Implementation of the
workaround reduces the rate of occurrence.
Workaround
TI recommends doing lock sequences in succession until the PLL is in locked state when
the PLL is configured for the first time after power up. The lock sequence is: disable the
PLL, start the PLL, wait for the LOCKS bit to set, and validate the PLL frequency using the
Dual Clock Comparator (DCC). After the PLL is observed to be running, it can be selected
as the CPU clock source.
TI recommends using the C2000Ware SysCtl_setClock() function, which also includes
implementation of this workaround, to set the PLL clock.
Details on DCC usage are in the C2000Ware SysCtl_IsPLLValid() function.
The workaround can also be applied at the system level by a supervisor resetting the
device if it is not responding.
Silicon Revision B Usage Notes and Advisories
18
TMS320F28004x Real-Time MCUs Silicon Errata
Silicon Revisions B, A, 0
SPRZ439G – JANUARY 2017 – REVISED AUGUST 2022
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