Texas Instruments TMS320F28004 Series, Manual

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Advisory GPIO: Signal Latch-up to V
SS
Revision Affected 0
Details The ESD structures on the pins listed below can be unintentionally turned on during
functional operation, which will pull the pins to V
SS
. There will be approximately 40 mA of
additional current on the V
DDIO
supply for each output pin in this condition.
• GPIO16
• GPIO17
• GPIO24
• GPIO25
• GPIO26
• GPIO27
• GPIO35 (TDI)
• GPIO37 (TDO)
• GPIO40
• GPIO41
• GPIO42
• GPIO43
The condition has not been observed below 70°C under normal operation. This condition
can occur in input or output mode and with any of the mux functions. Designs with lightly
loaded pins and fast switching signals are more likely to see the condition. Pins not
bonded out in smaller pin-count packages can also enter the latch-up condition if they are
toggled.
The latch-up condition can be ended by toggling the IO at a lower temperature.
Workarounds Four workaround options are:
1. Avoid using these pins on the revision affected.
2. Avoid high-temperature operations on the revision affected.
3. If the pin is configured as an input or output:
Place a capacitor of 300 pF or greater between each of these pins and ground,
placed as closely as possible to the device. This will slow down the fast signal and
avoid triggering the condition. Larger capacitors will be more effective at filtering the
transient but must be balanced against the system-level timing requirements of these
pins.
For input pins, a smaller capacitor may be possible when used in combination with
option 4.
4. If the pin is configured as an input:
Connect a resistor in series with any other components on the board such that the
total resistance of the driver plus the resistor is 1 kΩ or greater. The goal is to
eliminate fast voltage transient seen at the pin. This will also limit the DC current if the
ESD structure is activated due to noise.
Advisory ePWM: Event Latch (DCxEVTxLAT) of "DC Event-Based CBC Trip" May not Extend
Trigger Pulse as Expected When Asynchronous Path is Selected
Revision Affected 0
Details DCxEVTxLAT may lose the captured trigger event for an asynchronous input upon
deassertion. When an asynchronous trigger is deasserted, it is expected that the flop
holds the value until there is a Clear event. Since the trigger is asynchronous with
respect to the clock of the flop, there is a possibility that the flop may get cleared during
deassertion. This would result in a loss of event latch function.
Workaround None
www.ti.com Silicon Revision 0 Usage Notes and Advisories
SPRZ439G – JANUARY 2017 – REVISED AUGUST 2022
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TMS320F28004x Real-Time MCUs Silicon Errata
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