Texas Instruments TMS320F28004 Series, Manual

Page: 16 / 43

Advisory V
DD
Supply: During V
DDIO
Power Up, V
DD
May Also Rise
Revisions Affected 0, A, B
Details A leakage current from V
DDIO
to V
DD
is present when the V
DD
supply is below
approximately 0.5 V. This causes the V
DD
voltage to rise to approximately 0.5 V when
V
DDIO
is powered. This is observed when the device is configured to use either the
internal VREG (VREGENZ tied to V
SS
) or an external 1.2-V regulator (VREGENZ tied
to V
DDIO
), and there is a significant delay (about 1 ms) between the power up of V
DDIO
and V
DD
from external regulators or the ramp time of V
DDIO
is greater than 1 ms when in
internal VREG mode.
This does not impact device functionality once the external 1.2-V or internal 1.2-V supply
begins to ramp. See the
TMS320F28004x Real-Time Microcontrollers data sheet for
power sequencing requirements.
Workaround If this early voltage on V
DD
is a problem for system-level supervisor circuits, then minimize
the delay between ramping the 3.3-V V
DDIO
and 1.2-V V
DD
rails. If the internal VREG is
used, decrease the ramp time of the 3.3-V V
DDIO
supply to 1 ms or less.
Silicon Revision B Usage Notes and Advisories www.ti.com
16 TMS320F28004x Real-Time MCUs Silicon Errata
Silicon Revisions B, A, 0 SPRZ439G – JANUARY 2017 – REVISED AUGUST 2022
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