Interrupt Controller (NVIC)
ROM Location:
ROM_APITABLE
is an array of pointers located at
0x0100.0010
.
ROM_INTERRUPTTABLE
is an array of pointers located at
ROM_APITABLE[14]
.
ROM_IntPrioritySet
is a function pointer located at
ROM_INTERRUPTTABLE[6]
.
Parameters:
ui32Interrupt
specifies the interrupt in question.
ui8Priority
specifies the priority of the interrupt.
Description:
This function is used to set the priority of an interrupt. When multiple interrupts are asserted
simultaneously, the ones with the highest priority are processed before the lower priority in-
terrupts. Smaller numbers correspond to higher interrupt priorities; priority 0 is the highest
interrupt priority.
The hardware priority mechanism will only look at the upper 3 bits of the priority level, so
any prioritization must be performed in those bits. The remaining bits can be used to sub-
prioritize the interrupt sources, and may be used by the hardware priority mechanism on a
future part. This arrangement allows priorities to migrate to different NVIC implementations
without changing the gross prioritization of the interrupts.
Returns:
None.
144
April 8, 2013
Summary of Contents for Tiva TM4C123GH6PM
Page 26: ...Boot Loader 26 April 8 2013...
Page 68: ...Controller Area Network CAN 68 April 8 2013...
Page 122: ...Hibernation Module 122 April 8 2013...
Page 136: ...Inter Integrated Circuit I2C 136 April 8 2013...
Page 152: ...Memory Protection Unit MPU 152 April 8 2013...
Page 174: ...Pulse Width Modulator PWM Returns None 174 April 8 2013...
Page 196: ...Synchronous Serial Interface SSI 196 April 8 2013...
Page 222: ...System Control 222 April 8 2013...
Page 270: ...UART 270 April 8 2013...
Page 296: ...uDMA Controller 296 April 8 2013...
Page 351: ...April 8 2013 351...