Texas Instruments Tiva TM4C123GH6PM, User Manual

Page: 129 / 352

Inter-Integrated Circuit (I2C)
ROM Location:
ROM_APITABLE
is an array of pointers located at
0x0100.0010
.
ROM_I2CTABLE
is an array of pointers located at
ROM_APITABLE[3]
.
ROM_I2CMasterInitExpClk
is a function pointer located at
ROM_I2CTABLE[1]
.
Parameters:
ui32Base is the base address of the I2C Master module.
ui32I2CClk is the rate of the clock supplied to the I2C module.
bFast set up for fast data transfers
Description:
This function initializes operation of the I2C Master block. Upon successful initialization of the
I2C block, this function will have set the bus speed for the master, and will have enabled the
I2C Master block.
If the parameter bFast is true , then the master block is set up to transfer data at 400 kbps;
otherwise, it is set up to transfer data at 100 kbps.
The peripheral clock is the same as the processor clock. This is the value returned by
ROM_SysCtlClockGet() , or it can be explicitly hard-coded if it is constant and known (to save
the code/execution overhead of a call to ROM_SysCtlClockGet() ).
Returns:
None.
12.2.1.10 ROM_I2CMasterIntClear
Clears I2C Master interrupt sources.
Prototype:
void
ROM_I2CMasterIntClear(uint32_t ui32Base)
ROM Location:
ROM_APITABLE
is an array of pointers located at
0x0100.0010
.
ROM_I2CTABLE
is an array of pointers located at
ROM_APITABLE[3]
.
ROM_I2CMasterIntClear
is a function pointer located at
ROM_I2CTABLE[13]
.
Parameters:
ui32Base is the base address of the I2C Master module.
Description:
The I2C Master interrupt source is cleared, so that it no longer asserts. This must be done in
the interrupt handler to keep it from being called again immediately upon exit.
Note:
Because there is a write buffer in the Cortex-M4 processor, it may take several clock cycles
before the interrupt source is actually cleared. Therefore, it is recommended that the interrupt
source be cleared early in the interrupt handler (as opposed to the very last action) to avoid
returning from the interrupt handler before the interrupt source is actually cleared. Failure to
do so may result in the interrupt handler being immediately reentered (because the interrupt
controller still sees the interrupt source asserted).
Returns:
None.
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