Public Version
General-Purpose Memory Controller
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Bits
Field Name
Description
Type
Reset
11:10
DEVICETYPE
Selects the attached device type
RW
0x0
0x0: NOR Flash like, asynchronous and synchronous
devices
0x1: Reserved
0x2: NAND Flash like devices, stream mode
0x3: Reserved
9
MUXADDDATA
Enables the Address and data multiplexed protocol (Reset
RW
0x-
value is CS0MUXDEVICE input pin sampled at IC reset for
CS0 and 0 for CS1-7)
0x0: Non Multiplexed attached device
0x1: Address and data multiplexed attached device
8:5
RESERVED
Write 0s for future compatibility. Read returns 0s.
RW
0x0
4
TIMEPARAGRANULARITY
Signals timing latencies scalar factor (Rd/WrCycleTime,
RW
0x0
Rd/WrAccessTime, PageBurstAccessTime, CSOnTime,
CSRd/WrOffTime, ADVOnTime, ADVRd/WrOffTime,
OEOnTime, OEOffTime, WEOnTime, WEOffTime,
Cycle2CycleDelay, BusTurnAround, TimeOutStartValue)
0x0: x1 latencies
0x1: x2 latencies
3:2
RESERVED
Write 0s for future compatibility. Read returns 0s.
RW
0x0
1:0
GPMCFCLKDIVIDER
Divides the GPMC_FCLK clock
RW
0x0
0x0: GPMC_CLK frequency = GPMC_FCLK frequency
0x1: GPMC_CLK frequency = GPMC_FCLK frequency / 2
0x2: GPMC_CLK frequency = GPMC_FCLK frequency / 3
0x3: GPMC_CLK frequency = GPMC_FCLK frequency /4
Table 10-50. Register Call Summary for Register GPMC_CONFIG1_i
General-Purpose Memory Controller
•
:
•
Clocking, Reset, and Power Management Scheme
•
[2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
•
•
[15] [16] [17] [18] [19] [20] [21] [22] [23] [24]
•
:
[25] [26] [27] [28] [29] [30] [31] [32]
•
:
[33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [43] [44] [45] [46] [47] [48]
•
Asynchronous Access Description
:
[49] [50] [51] [52] [53] [54] [55] [56]
•
[57] [58] [59] [60] [61] [62] [63]
•
•
NAND Device Basic Programming Model
[65] [66] [67] [68] [69] [70] [71] [72] [73] [74] [75] [76] [77] [78] [79] [80] [81] [82] [83]
•
Table 10-51. GPMC_CONFIG2_i
Address Offset
0x0000 0064 + (0x0000 0030 * i)
Index
i = 0 to 7
Physical Address
0x6E00 0064 + (0x0000 0030 * i)
Instance
GPMC
Description
CS signal timing parameter configuration
Type
RW
2206
Memory Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated