GPMC_FCLK
GPMC_CLK
nBE1/nBE0
nCS
nADV
nOE
DIR
WAIT
Valid Address
Valid Address
Data 0
Data 0
OUT
IN
OUT
WaitPinMonitoring=01
WaitPinMonitoring=00
CSONTIME
CSRDOFFTIME
ADVONTIME
ADVRDOFFTIME
OEONTIME
OEOFFTIME
RDACCESSTIME
RDCYCLETIME
gpmc_a[11:1]
gpmc_d[15:0]
(connected to A[9:0] on
memory side)
(connected to D[15:0] on
memory side)
gpmc-008
Public Version
www.ti.com
General-Purpose Memory Controller
•
WAIT monitored as inactive unfreezes the CYCLETIME counter. For an access within a page, when
the CYCLETIME counter is by definition in a lock state, WAIT monitored as inactive completes the
current access time and starts the next access phase in the page. The data bus is considered valid,
and data are captured during this clock cycle. In case of a single access or if this was the last access
in a multiple-access cycle, all signals are controlled according to their related control timing value and
according to the CYCLETIME counter status.
When a delay larger than two GPMC clocks must be observed between wait-pin deactivation time and
data valid time (including the required GPMC and the device data setup time), an extra delay can be
added between wait-pin deassertion time detection and effective data-capture time and the effective
unlock of the CYCLETIME counter. This extra delay can be programmed in the
GPMC.
[19:18] WAITMONITORINGTIME field (i = 0 to 7).
NOTE:
•
The WAITMONITORINGTIME parameter does not delay the wait-pin active or inactive
detection, nor does it modify the two GPMC clocks pipelined detection delay.
•
This extra delay is expressed as a number of GPMC_CLK clock cycles, even though the
access is defined as asynchronous, and no GPMC_CLK clock is provided to the
external device. Still, GPMCFCLKDIVIDER is used as a divider for the GPMC clock, so
it must be programmed to define the correct WAITMONITORINGTIME delay.
shows wait behavior during an asynchronous single read access.
Figure 10-8. Wait Behavior During an Asynchronous Single Read Access (GPMCFCLKDivider = 1)
NOTE:
The WAIT signal is active low. WAITMONITORINGTIME = 00, 01.
2135
SWPU177N – December 2009 – Revised November 2010
Memory Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
