Texas Instruments OMAP36 Series, Technical Reference Manual

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FCLK
Data capture on GPMC side: AccessTime = 9
nADV
AdvRdOffTime = 1
RdCycleTime = 11
nCS
nOE
Valid Address A/D bus
CsReadOffTime = 10
OeOffTime = 10
OeOnTime = 3
Data Setup time
Data Hold time
tOEZ
Valid Address DATA
Memory-side access time
gpmc-01 1
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General-Purpose Memory Controller
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In the following section i stands for the chip-select number, i = 0 to 7.
• GPMC. GPMC_CONFIG [1] LIMITEDADDRESS set to 1 (A26-A11 are not modified during an external
memory access)
• GPMC. GPMC_CONFIG1_i register settings:
– GPMC_CONFIG1_i [30] READMULTIPLE bit at 0 (read single access)
– GPMC_CONFIG1_i [29] READTYPE bit at 0 (asynchronous read)
– GPMC_CONFIG1_i [9] MUXADDDATA bit at 0 (non multiplexed device)
• Chip-select signal nCS:
– nCS assertion time is controlled by the GPMC_CONFIG2_i [3:0] CSONTIME field. It controls the
address setup time to nCS assertion.
– nCS deassertion time is controlled by the GPMC_CONFIG2_i [12:8] CSRDOFFTIME field. It
controls the address hold time from nCS deassertion.
• Address valid signal nADV:
– nADV assertion time is controlled by the GPMC_CONFIG3_i [3:0] ADVONTIME field.
– nADV deassertion time is controlled by the GPMC_CONFIG3_i [12:8] ADVRDOFFTIME field.
• Output enable signal nOE:
– nOE assertion indicates a read cycle.
– nOE assertion time is controlled by the GPMC_CONFIG4_i [3:0] OEONTIME field.
– nOE deassertion time is controlled by the GPMC_CONFIG4_i [12:8] OEOFFTIME field.
• Read data is latched when RDACCESSTIME completes. Access time is defined in the
GPMC.
GPMC_CONFIG5_i [20:16] RDACCESSTIME field.
• The end of the access is defined by the RDCYCLETIME parameter. The read cycle time is defined in
the GPMC.
GPMC_CONFIG5_i [4:0] RDCYCLETIME field.
• Direction signal DIR: DIR goes from OUT to IN at the same time that nOE is asserted.
After a read operation, if no other access (read or write) is pending, the data bus is driven with the
previous read value. See
Section 10.1.5.3.10 , Bus Keeping Support for more details.
10.1.5.9.1.2 Asynchronous Single-Read Operation on an Address/Data Multiplexed Device
Figure 10-11 shows an asynchronous single read operation on an address/data-multiplexed device.
Figure 10-11. Asynchronous Single Read on an Address/Data-Multiplexed Device
When the GPMC generates a read access to an address/data-multiplexed device, it drives the address
bus until nOE assertion time. For details, see
Section 10.1.5.2.3 , Address/Data-Multiplexing Interface.
GPMC. GPMC_CONFIG1_i register settings (i = 0 to 7):
2142 Memory Subsystem SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated