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General-Purpose Memory Controller
Asynchronous and synchronous read (write) access time and related control signals are controlled through
timing parameters that refer to GPMC_FCLK. The primary difference of synchronous mode is the
availability of a configurable clock interface (GPMC_CLK) to control the external device. Synchronous
mode also affects data-capture and wait-pin monitoring schemes in read access.
For details about asynchronous and synchronous access, see the descriptions of GPMC_CLK,
RdAccessTime, WrAccessTime, and wait-pin monitoring.
For more information about timing-parameter settings, see the sample timing diagrams in this chapter.
NOTE:
The address bus and nBE[1:0] are fixed for the duration of a synchronous burst read
access, but they are updated for each beat of an asynchronous page-read access.
10.1.5.2.6 Page and Burst Support
Each chip-select can be configured to process system single or burst requests into successive single
accesses or asynchronous page/synchronous burst accesses, with appropriate access size adaptation.
Depending on the external device page or burst capability, read and write accesses can be independently
configured through the GPMC. The
[30] READMULTIPLE and
[28] WRITMULTIPLE bits (i = 0 to 7) are associated with the READTYPE and
WRITETYPE parameters.
NOTE:
•
Asynchronous write page mode is not supported.
•
8-bit wide device support is limited to nonburstable devices (READMULTIPLE and
WRITEMULTIPLE are don't care).
•
Not applicable to NAND device interfacing.
10.1.5.2.7 System Burst Versus External Device Burst Support
The device system can issue the following requests to the GPMC:
•
Byte, Word16, Word32 requests (byte enable controlled). This is always a single request from the
interconnect point of view.
•
Incrementing fixed-length bursts of two words, four words, and eight words
•
Wrapped (critical word access first) fixed-length burst of two, four, or eight words
To process a system request with the optimal protocol, the READMULTIPLE (and READTYPE) and
WRITEMULTIPLE (and WRITETYPE) parameters must be set according to the burstable capability
(synchronous or asynchronous) of the attached device.
The GPMC access engine issues only fixed-length burst. The maximum length that can be issued is
defined per CS by the GPMC.
[24:23] ATTACHEDDEVICEPAGELENGTH field (i = 0 to
7). When the ATTACHEDDEVICEPAGELENGTH value is less than the system burst request length
(including the appropriate access size adaptation according to the device width), the GPMC splits the
system burst request into multiple burst beats. Within the specified 4-, 8-, or 16-word value, the
ATTACHEDDEVICEPAGELENGTH field value must correspond to the maximum-length burst supported
by the memory device configured in fixed-length burst mode (as opposed to continuous burst mode).
To get optimal performance from memory devices that natively support 16 Word16-length-wrapping burst
capability (critical word access first), the ATTACHEDDEVICEPAGELENGTH parameter must be set to 16
words and the GPMC.
[31] WRAPBURST bit (i = 0 to 7) must be set to 1. Similarly
DEVICEPAGELENGTH is set to 4 and 8 for memories supporting respectively 4 and 8
Word16-length-wrapping burst.
When the memory device does not offer (or is not configured to offer) native 16 Word16-length-wrapping
burst, the WRAPBURST parameter must be cleared, and the GPMC access engine emulates the
wrapping burst by issuing the appropriate burst sequences according to the
ATTACHEDDEVICEPAGELENGTH value.
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SWPU177N – December 2009 – Revised November 2010
Memory Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
