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General-Purpose Memory Controller
•
The sys_boot[5] pin defines which group of booting sequences is preferred: memory booting
(sys_boot[5] = 0) or peripheral booting (sys_boot[5] = 1).
•
Three additional pins are used to configure reset values in the GPMC.
register
(where i = 0):
–
The bootwaiten input pin (GPMC boundary) enables the monitoring on chip-select 0 of the WAIT
pin at IC reset release time for read accesses. The input pin is used to configure the
GPMC.
[22] WAITREADMONITORING bit (where i = 0). Its value comes from
the BOOT_WAIT_ENABLE signal generated by the system control module (SCM). When
sys_boot[5:0] = 0b111111, the BOOT_WAIT_ENABLE signal is activated, causing the wait pin to
be monitored for read access.
–
The bootdevicesize input pin (GPMC boundary) defines the size of the attached device on
chip-select 0 and is used to configure the GPMC.
[13:12] DEVICESIZE bits
(where i = 0). A BOOT_DEVICE_SIZE signal is propagated from the SCM. Its value is fixed at 0x1
at IC reset, causing a 16-bit wide external memory to be used.
–
The cs0muxdevice input pin (GPMC boundary) selects whether the attached device to chip-select 0
is a multiplexed address and data device or not. The input pin is used to configure the
GPMC.
[9] MUXADDDATA bit (where i = 0). A CS0_MUX_DEVICE signal is
propagated from the SCM. Its value is fixed at 0x1 at IC reset, causing the attached device to be
address/data-multiplexed.
–
The waitselectpin input pin selects the WAIT signal at IC reset release time between WAIT0 input
pin or WAIT1 input pin. At IC reset release time, these two pins have different polarity.
CAUTION
Using the internal boot code, the entire CS0 configuration can be modified
before the first CS0 access. This modification of internal boot code is necessary
for two external devices:
•
NAND device attached to CS0
•
Nonmultiplexed 2-Kbyte address range device attached to CS0
At reset time, the IC may boot from the internal ROM or from the memory attached to the GPMC
chip-select 0. This selection is made outside the GPMC.
Reset values of the timing control parameters are defined to cope with direct boot on address and data
multiplexed NOR Flash device, on non-multiplexed NOR Flash device or on any asynchronous device with
large timing margins assuming a low GPMC_FCLK frequency (for example, 19.2Mhz) at boot time.
10.1.4 GPMC Functional Description
10.1.4.1 Description
As
shows, the GPMC consists of six blocks:
•
L3 interconnect port interface
•
Address decoder, GPMC configuration, and chip-select configuration register file
•
Access engine
•
Prefetch and write-posting engine
•
Error correction code engine (ECC)
•
External device/memory port interface
2121
SWPU177N – December 2009 – Revised November 2010
Memory Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
