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General-Purpose Memory Controller
The device system can issue the following requests through this interface:
•
One 8-bit/16-bit/32-bit interconnect access (read/write)
•
Two incrementing 32-bit interconnect accesses (read/write)
•
Two wrapped 32-bit interconnect accesses (read/write)
•
Four incrementing 32-bit interconnect accesses (read/write)
•
Four wrapped 32-bit interconnect accesses (read/write)
•
Eight incrementing 32-bit interconnect accesses (read/write)
•
Eight wrapped 32-bit interconnect accesses (read/write)
Only linear burst transactions are supported; interleaved burst transactions are not supported. Only
power-of-two-length precise bursts 2 * 32, 4 * 32, or 8 * 32 with the burst base address aligned on the
total burst size are supported (this limitation applies to incrementing bursts only).
This interface also provides one interrupt and one DMA request line, for specific event control.
It is recommended to program the ATTACHEDDEVICEPAGELENGTH field (
according to the effective attached device page length and to enable WRAPBURST bit
(
[31]) if the attached device supports wrapping burst.
However, it is possible to emulate wrapping burst on a non-wrapping memory by providing relevant
addresses within the page or splitting transactions. Bursts larger than the memory page length are
chopped into multiple bursts transactions. Due to the alignment requirements, a page boundary is never
crossed.
10.1.4.3 Address Decoder, GPMC Configuration, and Chip-Select Configuration Register File
Address-decoding logic selects for chip-selects according to the address request and the content of the
chip-select base address register file, which includes a set of global GPMC configuration registers and
eight sets of chip-select configuration registers.
The GPMC configuration register file is memory-mapped and can be read or written with byte, 16-bit word,
or 32-bit word accesses. The register file should be configured as a noncacheable, nonbufferable region
to prevent any desynchronization between host execution (write request) and the completion of register
configuration (write completed with register updated).
of this chapter provides the GPMC
register locations. For the map of GPMC memory locations, see
, Memory Mapping.
After the chip-select is configured, the access engine accesses the external device, drives the external
interface control signals, and applies the interface protocol based on user-defined timing parameters and
settings.
10.1.4.4 Error Correction Code Engine
The GPMC includes an error correction code (ECC) calculation engine that allows ECC calculation during
data read or data program (write) operations.Two ECC algorithms are available depending on
[16] ECCALGORITHM settings: Hamming code or BCH code
(Bose-ChaudhurI-Hocquenghem).
The GPMC does not directly handle the error code correction itself. During writes, the GPMC computes
parity bits. During reads, the GPMC provides enough information for the processor to correct errors
without reading the data buffer all over again.
The Hamming code ECC is based on a 2-dimensional (row and column) bit parity accumulation. This
parity accumulation is either accomplished on the programmed number of bytes or Word16s read from the
memory device, or written to the memory device in stream mode.
Because the ECC engine includes only one accumulation context, it can be allocated to only one
chip-select at a time through the GPMC.
[3:1] ECCCS bit field.
See
for more information on ECC calculation.
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SWPU177N – December 2009 – Revised November 2010
Memory Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
