Public Version
www.ti.com
General-Purpose Memory Controller
10.1.5.14.1.1 Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
The GPMC.
register (where i = 0 to 7) associated with a NAND device region
interfaced in byte or word stream mode can be initialized with a minimum size of 16 Mbytes, because any
address location in the chip-select memory region can be used to access a NAND data array. The NAND
Flash protocol specifies an address sequence where address bits are passed through the data bus in a
series of write accesses with the ALE pin asserted. After this address phase, all operations are streamed
and the system requests address is irrelevant.
CAUTION
To
allow
correct
command,
address,
and
data-access
controls,
the
register associated with a NAND device region
must be initialized in asynchronous read and write modes with the parameters
listed in
. Failure to comply with these settings corrupts the NAND
interface protocol.
Table 10-4. Chip-Select Configuration for NAND Interfacing
Bit Field
Register
Value
Comments
WRAPBURST
(1)
0
No wrap
READMULTIPLE
0
Single access
READTYPE
0
Asynchronous mode
WRITEMULTIPLE
0
Single access
WRITETYPE
0
Asynchronous mode
CLKACTIVATIONTIME
00
ATTACHEDDEVICEPAGELENGTH
Don't
Single-access mode
care
WAITREADMONITORING
0
Wait not monitored by GPMC access
engine
WAITWRITEMONITORING
0
Wait not monitored by GPMC access
engine
WAITMONITORINGTIME
Don't
Wait not monitored by GPMC access
care
engine
WAITPINSELECT
Select which wait is monitored by edge
detectors
DEVICESIZE
0b00 or
8- or 16-bit interface
0b01
DEVICETYPE
0b10
NAND device in stream mode
MUXADDDATA
0
Nonmultiplexed mode
TIMEPARAGRANULARITY
0
Timing achieved with best GPMC clock
granularity
GPMCFCLKDIVIDER
Don't
Asynchronous mode
care
(1)
i = 0 to 7
The GPMC.
to GPMC.
register (where i = 0 to 7) associated with a
NAND device region must be initialized with the correct control-signal timing value according to the NAND
device timing parameters.
10.1.5.14.1.2 NAND Device Command and Address Phase Control
NAND devices require multiple address programming phases. The CPU software driver is responsible for
issuing the correct number of command and address program accesses, according to the device
command set and the device address-mapping scheme.
2157
SWPU177N – December 2009 – Revised November 2010
Memory Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated