Texas Instruments OMAP36 Series, Technical Reference Manual

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General-Purpose Memory Controller
Bits Field Name Description Type Reset
19:16 WRDATAONADMUXBUS Specifies on which GPMC_FCLK rising edge the first data is RW 0x3
driven in the add/data mux bus
15:12 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0
11:8 CYCLE2CYCLEDELAY Chip-select high pulse delay between successive accesses RW 0x0
0x0: 0 GPMC_FCLK cycle
0x1: 1 GPMC_FCLK cycle
...
0xF: 15 GPMC_FCLK cycles
7 CYCLE2CYCLESAMECSEN Add CYCLE2CYCLEDELAY between successive accesses RW 0x0
to the same CS (any access type)
0x0: No delay between the two accesses
0x1: Add CYCLE2CYCLEDELAY
6 CYCLE2CYCLEDIFFCSEN Add CYCLE2CYCLEDELAY between successive accesses RW 0x0
to a different CS (any access type)
0x0: No delay between the two accesses
0x1: Add CYCLE2CYCLEDELAY
5:4 RESERVED Write 0s for future compatibility. RW 0x0
Reads returns 0
3:0 BUSTURNAROUND Bus turn around latency between successive accesses to RW 0x0
the same CS (read to write) or to a different CS (read to
read and read to write)
0x0: 0 GPMC_FCLK cycle
0x1: 1 GPMC_FCLK cycle
...
0xF: 15 GPMC_FCLK cycles
Table 10-60. Register Call Summary for Register GPMC_CONFIG6_i
General-Purpose Memory Controller
• Timing Setting : [0] [1] [2] [3]
• WAIT Pin Monitoring Control : [4] [5] [6] [7] [8]
• Asynchronous Access Description : [9] [10] [11]
• Synchronous Access : [12] [13] [14]
• GPMC Register Summary : [15]
Table 10-61. GPMC_CONFIG7_i
Address Offset 0x0000 0078 + (0x0000 0030 * i) Index i = 0 to 7
Physical Address 0x6E00 0078 + (0x0000 0030 * i) Instance GPMC
Description CS address mapping configuration
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED BASEADDRESS
CSVALID
RESERVED
MASKADDRESS
2211 SWPU177N – December 2009 – Revised November 2010 Memory Subsystem
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