GPMC_FCLK
GPMC_CLK
gpmc_a[11:1]
gpmc_d[15:0]
nBE1/nBE0
nCS
nADV
nOE
WAIT
Valid Address
Data 0
Data 0
CSONTIME
CSRDOFFTIME
ADVONTIME
ADVRDOFFTIME
OEONTIME
OEOFFTIME
RDACCESSTIME
RDCYCLETIME
(connected to A[10:1] on
memory side)
(connected to D[15:0] on
memory side)
gpmc-007
Public Version
www.ti.com
General-Purpose Memory Controller
Figure 10-7. Asynchronous Single Read on a Nonmultiplexed Address/Data Device
10.1.5.3.1 Read Cycle Time and Write Cycle Time (RDCYCLETIME/WRCYCLETIME)
The GPMC.
[4:0] RDCYCLETIME and GPMC.
[12:8]
WRCYCLETIME fields (i = 0 to 7) define the address bus and byte enables valid times for read and write
accesses. To ensure a correct duty cycle of GPMC_CLK between accesses, RDCYCLETIME and
WRCYCLETIME are expressed in GPMC_FCLK cycles and must be multiples of the GPMC_CLK cycle.
When either RDCYCLETIME or WRCYCLETIME completes, if they are not already deasserted, all control
signals (NCS, nADV/ALE, nOE/RE, nWE, and BE0/CLE) are deasserted to their reset values, regardless
of their deassertion time parameters.
An exception to this forced deassertion occurs when a pipelined request to the same chip-select or to a
different chip-select is pending. In such a case, it is not necessary to deassert a control signal with
deassertion time parameters equal to the cycle-time parameter. This exception to forced deassertion
prevents any unnecessary glitchy transition. This requirement also applies to BE signals, thus avoiding an
unnecessary BE glitch transition when pipelining requests.
If no inactive cycles are required between successive accesses to the same or to a different chip-select
(GPMC.
[7] CYCLE2CYCLESAMECSEN = 0 or GPMC.
CYCLE2CYCLEDIFFCSEN = 0, where i = 0 to 7), and if assertion-time parameters associated with the
pipelined access are equal to 0, asserted control signals (nCS, nADV/ALE, nBE0/CLE, nWE, and
nOE/RE) are kept asserted. This applies to any read/write to read/write access combination.
If inactive cycles are inserted between successive accesses, that is, CYCLE2CYCLESAMECSEN = 1 or
CYCLE2CYCLEDIFFCSEN = 1, the control signals are forced to their respective default reset values for
the number of GPMC_FCLK cycles defined in CYCLE2CYCLEDELAY:
2129
SWPU177N – December 2009 – Revised November 2010
Memory Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
