Public Version
General-Purpose Memory Controller
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Bits
Field Name
Description
Type
Reset
23:21
RESERVED
Write 0s for future compatibility. Read returns 0s.
RW
0x0
20:16
RDACCESSTIME
Delay between start cycle time and first data valid
RW
0x0F
0x00: 0 GPMC_FCLK cycle
0x01: 1 GPMC_FCLK cycle
...
0x1F: 31 GPMC_FCLK cycles
15:13
RESERVED
Write 0s for future compatibility.
RW
0x0
Reads returns 0
12:8
WRCYCLETIME
Total write cycle time
RW
0x11
0x00: 0 GPMC_FCLK cycle
0x01: 1 GPMC_FCLK cycle
...
0x1F: 31 GPMC_FCLK cycles
7:5
RESERVED
Write 0s for future compatibility. Read returns 0s.
RW
0x0
4:0
RDCYCLETIME
Total read cycle time
RW
0x11
0x00: 0 GPMC_FCLK cycle
0x01: 1 GPMC_FCLK cycle
...
0x1F: 31 GPMC_FCLK cycles
Table 10-58. Register Call Summary for Register GPMC_CONFIG5_i
General-Purpose Memory Controller
•
:
•
Asynchronous Access Description
:
•
•
Table 10-59. GPMC_CONFIG6_i
Address Offset
0x0000 0074 + (0x0000 0030 * i)
Index
i = 0 to 7
Physical Address
0x6E00 0074 + (0x0000 0030 * i)
Instance
GPMC
Description
WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle and BusTurnAround parameters configuration
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
WRACCESSTIME
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
BUSTURNAROUND
CYCLE2CYCLEDELAY
WRDATAONADMUXBUS
CYCLE2CYCLEDIFFCSEN
CYCLE2CYCLESAMECSEN
Bits
Field Name
Description
Type
Reset
31
RESERVED
TI Internal use - Do not modify.
RW
0x1
30:29
RESERVED
Write 0s for future compatibility. Read returns 0s.
RW
0x0
28:24
WRACCESSTIME
Delay from start access time to the GPMC_FCLK rising
RW
0x0F
edge corresponding the the GPMC_CLK rising edge used
by the attached memory for the first data capture
0x00: 0 GPMC_FCLK cycle
0x01: 1 GPMC_FCLK cycle
...
0x1F: 31 GPMC_FCLK cycles
23:20
RESERVED
Write 0s for future compatibility. Read returns 0s.
RW
0x0
2210
Memory Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated