GPMC_FCLK
GPMC_CLK
WAIT
Valid Address
D 0
CSONTIME
ADVONTIME
ADVRDOFFTIME
OEONTIME
OEOFFTIME
CLKACTIVATIONTIME
CSRDOFFTIME
RDCYCLETIME
RDACCESSTIME
nBE1/nBE0
nCS
nADV
nOE
gpmc_a[11:1]
gpmc_d[15:0]
(connected to A[9:0] on
memory side)
(connected to D[15:0] on
memory side)
gpmc-016
Public Version
www.ti.com
General-Purpose Memory Controller
Figure 10-16. Synchronous Single Read (GPMCFCLKDIVIDER = 1)
In the following section i stands for the chip-select number, i = 0 to 7.
•
GPMC.
register settings:
–
READMULTIPLE bit at 0 (read single access)
–
READTYPE bit at 1 (read synchronous)
–
MUXADDDATA bit at 0 (non-address/data-multiplexed device)
•
Chip-select signal nCS:
–
nCS assertion time is controlled by the GPMC.
[3:0] CSONTIME field and
ensures address setup time to nCS assertion.
–
nCS deassertion time is controlled by the GPMC.
[12:8] CSRDOFFTIME field
and ensures address hold time to nCS deassertion.
•
Address valid signal nADV:
–
nADV assertion time is controlled by the GPMC.
[3:0] ADVONTIME field.
–
nADV deassertion time is controlled by the GPMC.
[12:8] ADVRDOFFTIME
field.
•
Output enable signal nOE:
–
nOE assertion indicates a read cycle.
–
nOE assertion time is controlled by the GPMC.
[3:0] OEONTIME field.
–
nOE deassertion time is controlled by the GPMC.
[12:8] OEOFFTIME field.
•
Initial latency for the first read data is controlled by GPMC.
[20:16]
RDACCESSTIME or by monitoring the WAIT signal.
2149
SWPU177N – December 2009 – Revised November 2010
Memory Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated