GPMC_FCLK
GPMC_CLK
WAIT
Valid Address
Write Data
CSONTIME
CSWROFFTIME
ADVONTIME
ADVWROFFTIME
WEONTIME
WEOFFTIME
WRCYCLETIME
nBE1/nBE0
nCS
nADV
nWE
gpmc_a[11:1]
gpmc_d[15:0]
(connected to A[10:1]] on
memory side)
(connected to D[15:0] on
memory side)
gpmc-012
Public Version
General-Purpose Memory Controller
www.ti.com
10.1.5.9.2 Asynchronous Single Write
10.1.5.9.2.1 Asynchronous Single Write Operation on a Nonmultiplexed Device
shows an asynchronous single write operation on a nonmultiplexed device.
Figure 10-12. Asynchronous Single Write on an Address/Data-Nonmultiplexed Device
In the following section i stands for the chip-select number, i = 0 to 7.
•
GPMC.
[1] LIMITEDADDRESS set to 1 (A26-A11 are not modified during an external
memory access)
•
GPMC.
register settings:
–
WRITEMULTIPLE bit at 0 (write single access)
–
WRITETYPE bit at 0 (write asynchronous)
–
MUXADDDATA bit at 0 (nonaddress/data-multiplexed device)
•
Chip-select signal nCS:
–
nCS assertion time is controlled by the GPMC.
[3:0] CSONTIME field and
ensures address setup time to nCS assertion.
–
nCS deassertion time is controlled by the GPMC.
[20:16] CSWROFFTIME field
and ensures address hold time to nCS deassertion.
•
Address valid signal nADV:
–
nADV assertion time is controlled by the GPMC.
[3:0] ADVONTIME field.
–
nADV deassertion time is controlled by the GPMC.
[20:16] ADVWROFFTIME
field.
Address and data are driven on their corresponding buses at start-of-cycle time.
•
Write enable signal nWE:
–
nWE assertion indicates a write cycle.
–
nWE assertion time is controlled by the GPMC.
[19:16] WEONTIME field.
–
nWE deassertion time is controlled by the GPMC.
[28:24] WEOFFTIME field.
•
Direction signal DIR:
DIR signal is OUT during the entire access.
2144
Memory Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated