Texas Instruments OMAP36 Series, Technical Reference Manual

Page: 1921 / 3738

Public Version
www.ti.com
Display Subsystem Register Manual
Bits Field Name Description Type Reset
10:8 DATA2_POSITION Position and order of the DATA lane 2. RW 0x0
0x0: Not used/connected
0x1: Data lane 2 is at the position 1 (line 1).
0x2: Data lane 2 is at the position 2 (line 2).
0x3: Data lane 2 is at the position 3 (line 3).
Other values: reserved
7 DATA1_POL +/- differential pin order of DATA lane 1 RW 0x0
0x0: +/- pin order ( and dsi_dy=-)
0x1: -/+ pin order (dsi_dx=- and )
6:4 DATA1_POSITION Position and order of the DATA lane 1. RW 0x0
0x1: Data lane 1 is at the position 1 (line 1).
0x2: Data lane 1 is at the position 2 (line 2).
0x3: Data lane 1 is at the position 3 (line 3).
Other values: reserved
3 CLOCK_POL +/- differential pin order of CLOCK lane. RW 0x0
0x0: +/- pin order ( and dsi_dy=-)
0x1: -/+ pin order (dsi_dx=- and )
2:0 CLOCK_POSITION Position and order of the CLOCK lane. RW 0x0
The clock lane is always present.
0x1: Clock lane is at the position 1 (line 1).
0x2: Clock lane is at the position 2 (line 2).
0x3: Clock lane is at the position 3 (line 3).
Other values: reserved
Table 7-381. Register Call Summary for Register DSI_COMPLEXIO_CFG1
Display Subsystem Environment
• Data/Clock Configuration : [0] [1]
Display Subsystem Functional Description
• DSI Protocol Architecture : [2]
• Shadowing Register : [3] [4] [5] [6] [7] [8] [9]
• Complex I/O Power FSM : [10] [11]
Display Subsystem Basic Programming Model
• Exiting ULPS : [12] [13]
• Software Reset : [14]
• Pad Configuration : [15] [16] [17]
Display Subsystem Use Cases and Tips
• Set Up DSI Control Registers : [18] [19] [20]
• Configure DSI Protocol Engine : [21] [22] [23] [24] [25] [26]
Display Subsystem Register Manual
• DSI Protocol Engine Register Mapping Summary : [27]
1921 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated