ULPS
ON
OFF
RESET
DSI_COMPLEXIO_CFG1
PWR_CMD = 0X0
[28:27]
DSI_COMPLEXIO_CFG1[28:27] PWR_CMD = 0x1
DSI_COMPLEXIO_CFG1
PWR_CMD = 0x0
[28:27]
DSI_COMPLEXIO_CFG1
PWR_CMD = 0x2
[28:27]
DSI_COMPLEXIO_CFG1
PWR_CMD = 0x1
[28:27]
dss-169
Public Version
Display Subsystem Functional Description
www.ti.com
7.4.3.6.1.2 Complex I/O Power FSM
describes the power control FSM to control the power state of the complex I/O.
Figure 7-93. Complex I/O Power FSM
The PwrCmdOff, PwrCmdUlp and PwrCmdOn commands control the state transition of the DSI complex
I/O. Software users must set the DSS.
[28:27] PWR_CMD bit field to ask for a
state change. The allowed transitions are: OFF -> ON and ON -> ULP and ULP -> OFF. The
DSS.
[26:25] PWR_STATUS bit field gives a status on the current state of the
DSI complex I/O.
CAUTION
•
In automatic mode, software must ensure that the DSI complex I/O in the
ON mode (that is, ON command already sent) before sending requests to
the complex I/O.
•
In a command request to change to a state which is the current one
(acknowledge has been received), the command is ignored (nothing is sent
to the DSI complex I/O).
•
To change state to ULP state, users must ensure that all the three
ULPSActiveNot signals are low. The ULPSActiveNot_ALL0_IRQ interrupt
can be used by software users to determine the state of the ULPSActiveNot
signals. The change from ULP to ON state is required before starting the
ULP status exit sequence (see
for details).
7.4.3.6.2 DSI PLL Power Control Commands
The DSI PLL controller module can be set into four modes:
•
OFF: The DSI PLL and HSDIVIDER are OFF.
•
ON ALL: Both DSI PLL and HSDIVIDER are ON. The HS_CLK clock is provided to the DSI complex
I/O and the second clock output is provided to the HSDIVIDER.
•
ON HSCLK: The DSI PLL is ON. The HSDIVIDER is OFF. The HS_CLK clock is provided to the DSI
complex I/O but the second clock output is not provided to the HSDIVIDER.
•
ON DIV: Both DSI PLL and HSDIVIDER are ON. The HS_CLK clock is not provided to the DSI
complex I/O but the second clock output is provided to the HSDIVIDER.
1672
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
