Texas Instruments MSP50C6xx, User Manual

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Memory Organization: RAM and ROM
2-19 MSP50C6xx Architecture
The branch to the program location that is specified in the interrupt vector is,
of course, contingent on the occurrence of the trigger event. Refer to Section
3.1.5, Internal and External Interrupts, for more information regarding the
specific conditions for each interrupt-trigger event. The branch operation,
however, is also contingent on whether the interrupt service has been enabled.
This is done individually for each interrupt, using the interrupt mask bits within
the interrupt/general control register. Refer to Section 2.7, Interrupt Logic, for
more details.
The ROM location 0x7FFF holds the program destination associated with the
hardware RESET event (branch happens after RESET LOW-to-HIGH). The
location 0x7FFE holds the read/write block-protection word. Refer to Sec-
tion 2.6.4, ROM Code Security, for an explanation of the ROM security
scheme.
2.6.4 ROM Code Security
The C6xx provides a mechanism for protecting its internal ROM code from
third-party pirating. The protection scheme is composed of two levels, both of
which prevent the ROM contents from being read. Protection may be applied
to the entire program memory, or it can be applied to a block of memory
beginning at address 0x0000 and ending at an arbitrary address. The two
levels of ROM protection are designated as follows:
-
Direct read and write protection, via the ROM scan circuit.
-
Indirect read protection, which prohibits the execution of memory-lookup
instructions.
For the purposes of direct security, the ROM is divided into two blocks. The first
block begins at location 0x0000, and ends, inclusively, at location
(m
×
512 – 1), where m is some integer. Each address specifies a 17-bit word
location. The second block begins at location (m
×
512), and ends, inclusively,
at 0x7FFF (the end of the ROM). The first block is protected from reads and
writes by programming a block protection bit, and the second block is
protected from reads and writes by programming a global protection bit.
The two-block system is designed in such a way that a secondary developer
is prevented from changing the partition address between blocks. Once the
block protection has been engaged, then the only security option available to
the secondary developer is engaging the global protection.